3f1923384032b90db1235d4730a1e6f3eab61a61
[ieee754fpu.git] / src / ieee754 / fpdiv / test / test_div.py
1 import sys
2 from random import randint
3 from random import seed
4 from operator import truediv
5
6 from nmigen import Module, Signal
7 from nmigen.compat.sim import run_simulation
8
9 from nmigen_div_experiment import FPDIV
10
11 from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
12 is_inf, is_pos_inf, is_neg_inf,
13 match, get_case, check_case, run_test,
14 run_edge_cases, run_corner_cases)
15
16
17 def testbench(dut):
18 yield from check_case(dut, 0x80000000, 0x00000000, 0xffc00000)
19 yield from check_case(dut, 0x00000000, 0x80000000, 0xffc00000)
20 yield from check_case(dut, 0x0002b017, 0xff3807ab, 0x80000000)
21 yield from check_case(dut, 0x40000000, 0x3F800000, 0x40000000)
22 yield from check_case(dut, 0x3F800000, 0x40000000, 0x3F000000)
23 yield from check_case(dut, 0x3F800000, 0x40400000, 0x3EAAAAAB)
24 yield from check_case(dut, 0x40400000, 0x41F80000, 0x3DC6318C)
25 yield from check_case(dut, 0x41F9EB4D, 0x429A4C70, 0x3ECF52B2)
26 yield from check_case(dut, 0x7F7FFFFE, 0x70033181, 0x4EF9C4C8)
27 yield from check_case(dut, 0x7F7FFFFE, 0x70000001, 0x4EFFFFFC)
28 yield from check_case(dut, 0x7F7FFCFF, 0x70200201, 0x4ECCC7D5)
29 yield from check_case(dut, 0x70200201, 0x7F7FFCFF, 0x302003E2)
30
31 count = 0
32
33 #regression tests
34 stimulus_a = [0xbf9b1e94, 0x34082401, 0x5e8ef81, 0x5c75da81, 0x2b017]
35 stimulus_b = [0xc038ed3a, 0xb328cd45, 0x114f3db, 0x2f642a39, 0xff3807ab]
36 yield from run_test(dut, stimulus_a, stimulus_b, truediv, get_case)
37 count += len(stimulus_a)
38 print (count, "vectors passed")
39
40 yield from run_corner_cases(dut, count, truediv, get_case)
41 yield from run_edge_cases(dut, count, truediv, get_case)
42
43
44 if __name__ == '__main__':
45 dut = FPDIV(width=32)
46 run_simulation(dut, testbench(dut), vcd_name="test_div.vcd")
47