src/ieee754/fpmul/mul1.py

   1 # IEEE Floating Point Multiplier
   2
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmigen.cli import main, verilog
   5
   6 from ieee754.fpcommon.fpbase import FPState
   7 from ieee754.fpcommon.postcalc import FPAddStage1Data
   8 from .mul0 import FPMulStage0Data
   9
  10
  11 class FPMulStage1Mod(FPState, Elaboratable):
  12     """ Second stage of mul: preparation for normalisation.
  13         detects when tot sum is too big (tot[27] is kinda a carry bit)
  14     """
  15
  16     def __init__(self, width, id_wid):
  17         self.width = width
  18         self.id_wid = id_wid
  19         self.i = self.ispec()
  20         self.o = self.ospec()
  21
  22     def ispec(self):
  23         return FPMulStage0Data(self.width, self.id_wid)
  24
  25     def ospec(self):
  26         return FPAddStage1Data(self.width, self.id_wid)
  27
  28     def process(self, i):
  29         return self.o
  30
  31     def setup(self, m, i):
  32         """ links module to inputs and outputs
  33         """
  34         m.submodules.mul1 = self
  35         m.submodules.mul1_out_overflow = self.o.of
  36
  37         m.d.comb += self.i.eq(i)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41         m.d.comb += self.o.z.eq(self.i.z)
  42         # tot[-1] (MSB) gets set when the sum overflows. shift result down
  43         with m.If(~self.i.out_do_z):
  44             mw = self.o.z.m_width
  45             m.d.comb += [
  46                 self.o.z.m.eq(self.i.product[mw+2:]),
  47                 self.o.of.m0.eq(self.i.tot[mw+2]),
  48                 self.o.of.guard.eq(self.i.tot[mw+1]),
  49                 self.o.of.round_bit.eq(self.i.tot[mw]),
  50                 self.o.of.sticky.eq(self.i.tot[0:mw].bool())
  51             ]
  52
  53         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  54         m.d.comb += self.o.oz.eq(self.i.oz)
  55         m.d.comb += self.o.mid.eq(self.i.mid)
  56
  57         return m
  58
  59
  60 class FPMulStage1(FPState):
  61
  62     def __init__(self, width, id_wid):
  63         FPState.__init__(self, "multiply_1")
  64         self.mod = FPMulStage1Mod(width)
  65         self.out_z = FPNumBase(width, False)
  66         self.out_of = Overflow()
  67         self.norm_stb = Signal()
  68
  69     def setup(self, m, i):
  70         """ links module to inputs and outputs
  71         """
  72         self.mod.setup(m, i)
  73
  74         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in mul1 state
  75
  76         m.d.sync += self.out_of.eq(self.mod.out_of)
  77         m.d.sync += self.out_z.eq(self.mod.out_z)
  78         m.d.sync += self.norm_stb.eq(1)
  79
  80     def action(self, m):
  81         m.next = "normalise_1"
  82