src/ieee754/fpmul/mul1.py

   1 # IEEE Floating Point Multiplier
   2
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmigen.cli import main, verilog
   5
   6 from ieee754.fpcommon.fpbase import FPState
   7 from ieee754.fpcommon.postcalc import FPAddStage1Data
   8 from .mul0 import FPMulStage0Data
   9
  10
  11 class FPMulStage1Mod(FPState, Elaboratable):
  12     """ Second stage of mul: preparation for normalisation.
  13     """
  14
  15     def __init__(self, width, id_wid):
  16         self.width = width
  17         self.id_wid = id_wid
  18         self.i = self.ispec()
  19         self.o = self.ospec()
  20
  21     def ispec(self):
  22         return FPMulStage0Data(self.width, self.id_wid)
  23
  24     def ospec(self):
  25         return FPAddStage1Data(self.width, self.id_wid)
  26
  27     def process(self, i):
  28         return self.o
  29
  30     def setup(self, m, i):
  31         """ links module to inputs and outputs
  32         """
  33         m.submodules.mul1 = self
  34         m.submodules.mul1_out_overflow = self.o.of
  35
  36         m.d.comb += self.i.eq(i)
  37
  38     def elaborate(self, platform):
  39         m = Module()
  40         m.d.comb += self.o.z.eq(self.i.z)
  41         with m.If(~self.i.out_do_z):
  42             mw = self.o.z.m_width
  43             m.d.comb += [
  44                 self.o.z.m.eq(self.i.product[mw+2:]),
  45                 self.o.of.m0.eq(self.i.product[mw+2]),
  46                 self.o.of.guard.eq(self.i.product[mw+1]),
  47                 self.o.of.round_bit.eq(self.i.product[mw]),
  48                 self.o.of.sticky.eq(self.i.product[0:mw].bool())
  49             ]
  50
  51         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  52         m.d.comb += self.o.oz.eq(self.i.oz)
  53         m.d.comb += self.o.mid.eq(self.i.mid)
  54
  55         return m
  56
  57
  58 class FPMulStage1(FPState):
  59
  60     def __init__(self, width, id_wid):
  61         FPState.__init__(self, "multiply_1")
  62         self.mod = FPMulStage1Mod(width)
  63         self.out_z = FPNumBase(width, False)
  64         self.out_of = Overflow()
  65         self.norm_stb = Signal()
  66
  67     def setup(self, m, i):
  68         """ links module to inputs and outputs
  69         """
  70         self.mod.setup(m, i)
  71
  72         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in mul1 state
  73
  74         m.d.sync += self.out_of.eq(self.mod.out_of)
  75         m.d.sync += self.out_z.eq(self.mod.out_z)
  76         m.d.sync += self.norm_stb.eq(1)
  77
  78     def action(self, m):
  79         m.next = "normalise_1"
  80