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[ieee754fpu.git] / src / nmutil / concurrentunit.py
1 """ concurrent unit from mitch alsup augmentations to 6600 scoreboard
2
3 * data fans in
4 * data goes through a pipeline
5 * results fan back out.
6
7 the output data format has to have a member "muxid", which is used
8 as the array index on fan-out
9 """
10
11 from math import log
12 from nmigen import Module, Elaboratable
13 from nmigen.cli import main, verilog
14
15 from nmutil.singlepipe import PassThroughStage
16 from nmutil.multipipe import CombMuxOutPipe
17 from nmutil.multipipe import PriorityCombMuxInPipe
18
19
20 def num_bits(n):
21 return int(log(n) / log(2))
22
23
24 class FPADDInMuxPipe(PriorityCombMuxInPipe):
25 def __init__(self, num_rows, iospecfn, maskwid=0):
26 self.num_rows = num_rows
27 stage = PassThroughStage(iospecfn)
28 PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows,
29 maskwid=maskwid)
30
31
32 class FPADDMuxOutPipe(CombMuxOutPipe):
33 def __init__(self, num_rows, iospecfn, maskwid=0):
34 self.num_rows = num_rows
35 stage = PassThroughStage(iospecfn)
36 CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows,
37 maskwid=maskwid)
38
39
40 class ReservationStations(Elaboratable):
41 """ Reservation-Station pipeline
42
43 Input: num_rows - number of input and output Reservation Stations
44
45 Requires: the addition of an "alu" object, from which ispec and ospec
46 are taken, and inpipe and outpipe are connected to it
47
48 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
49 * ALU pipeline
50 * fan-out on outputs (an array of FPPackData: z,mid)
51
52 Fan-in and Fan-out are combinatorial.
53 """
54 def __init__(self, num_rows, maskwid=0):
55 self.num_rows = nr = num_rows
56 self.inpipe = FPADDInMuxPipe(nr, self.i_specfn, maskwid) # fan-in
57 self.outpipe = FPADDMuxOutPipe(nr, self.o_specfn, maskwid) # fan-out
58
59 self.p = self.inpipe.p # kinda annoying,
60 self.n = self.outpipe.n # use pipe in/out as this class in/out
61 self._ports = self.inpipe.ports() + self.outpipe.ports()
62
63 def elaborate(self, platform):
64 m = Module()
65 m.submodules.inpipe = self.inpipe
66 m.submodules.alu = self.alu
67 m.submodules.outpipe = self.outpipe
68
69 m.d.comb += self.inpipe.n.connect_to_next(self.alu.p)
70 m.d.comb += self.alu.connect_to_next(self.outpipe)
71
72 return m
73
74 def ports(self):
75 return self._ports
76
77 def i_specfn(self):
78 return self.alu.ispec()
79
80 def o_specfn(self):
81 return self.alu.ospec()