src/nmutil/latch.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Signal, Module, Elaboratable
   4
   5 """ jk latch
   6
   7 module jk(q,q1,j,k,c);
   8 output q,q1;
   9 input j,k,c;
  10 reg q,q1;
  11 initial begin q=1'b0; q1=1'b1; end
  12 always @ (posedge c)
  13   begin
  14     case({j,k})
  15          {1'b0,1'b0}:begin q=q; q1=q1; end
  16          {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
  17          {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
  18          {1'b1,1'b1}: begin q=~q; q1=~q1; end
  19     endcase
  20    end
  21 endmodule
  22 """
  23
  24 class SRLatch(Elaboratable):
  25     def __init__(self, sync=True):
  26         self.sync = sync
  27         self.s = Signal(reset_less=True)
  28         self.r = Signal(reset_less=True)
  29         self.q = Signal(reset_less=True)
  30         self.qn = Signal(reset_less=True)
  31
  32     def elaborate(self, platform):
  33         m = Module()
  34         q_int = Signal(reset_less=True)
  35
  36         if self.sync:
  37             with m.If(self.s):
  38                 m.d.sync += q_int.eq(1)
  39             with m.Elif(self.r):
  40                 m.d.sync += q_int.eq(0)
  41             with m.Else():
  42                 m.d.sync += q_int.eq(q_int)
  43             m.d.comb += self.q.eq(q_int)
  44         else:
  45             with m.If(self.s):
  46                 m.d.sync += q_int.eq(1)
  47                 m.d.comb += self.q.eq(1)
  48             with m.Elif(self.r):
  49                 m.d.sync += q_int.eq(0)
  50                 m.d.comb += self.q.eq(0)
  51             with m.Else():
  52                 m.d.sync += q_int.eq(q_int)
  53                 m.d.comb += self.q.eq(q_int)
  54         m.d.comb += self.qn.eq(~self.q)
  55
  56         return m
  57
  58     def ports(self):
  59         return self.s, self.r, self.q, self.qn
  60
  61
  62 def sr_sim(dut):
  63     yield dut.s.eq(0)
  64     yield dut.r.eq(0)
  65     yield
  66     yield
  67     yield
  68     yield dut.s.eq(1)
  69     yield
  70     yield
  71     yield
  72     yield dut.s.eq(0)
  73     yield
  74     yield
  75     yield
  76     yield dut.r.eq(1)
  77     yield
  78     yield
  79     yield
  80     yield dut.r.eq(0)
  81     yield
  82     yield
  83     yield
  84
  85 def test_sr():
  86     dut = SRLatch()
  87     vl = rtlil.convert(dut, ports=dut.ports())
  88     with open("test_srlatch.il", "w") as f:
  89         f.write(vl)
  90
  91     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd')
  92
  93     dut = SRLatch(sync=False)
  94     vl = rtlil.convert(dut, ports=dut.ports())
  95     with open("test_srlatch_async.il", "w") as f:
  96         f.write(vl)
  97
  98     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch_async.vcd')
  99
 100 if __name__ == '__main__':
 101     test_sr()