src/scoreboard/dependence_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class DependenceCell(Elaboratable):
   8     """ implements 11.4.7 mitch alsup dependence cell, p27
   9     """
  10     def __init__(self):
  11         # inputs
  12         self.dest_i = Signal(reset_less=True)     # Dest in (top)
  13         self.src1_i = Signal(reset_less=True)     # oper1 in (top)
  14         self.src2_i = Signal(reset_less=True)     # oper2 in (top)
  15         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  16
  17         self.go_write_i = Signal(reset_less=True) # Go Write in (left)
  18         self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
  19
  20         # for Register File Select Lines (vertical)
  21         self.dest_rsel_o = Signal(reset_less=True)  # dest reg sel (bottom)
  22         self.src1_rsel_o = Signal(reset_less=True)  # src1 reg sel (bottom)
  23         self.src2_rsel_o = Signal(reset_less=True)  # src2 reg sel (bottom)
  24
  25         # for Function Unit "forward progress" (horizontal)
  26         self.dest_fwd_o = Signal(reset_less=True)   # dest FU fw (right)
  27         self.src1_fwd_o = Signal(reset_less=True)   # src1 FU fw (right)
  28         self.src2_fwd_o = Signal(reset_less=True)   # src2 FU fw (right)
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         m.submodules.dest_l = dest_l = SRLatch()
  33         m.submodules.src1_l = src1_l = SRLatch()
  34         m.submodules.src2_l = src2_l = SRLatch()
  35
  36         # destination latch: reset on go_write HI, set on dest and issue
  37         m.d.sync += dest_l.s.eq(self.issue_i & self.dest_i)
  38         m.d.sync += dest_l.r.eq(self.go_write_i)
  39
  40         # src1 latch: reset on go_read HI, set on src1_i and issue
  41         m.d.sync += src1_l.s.eq(self.issue_i & self.src1_i)
  42         m.d.sync += src1_l.r.eq(self.go_read_i)
  43
  44         # src2 latch: reset on go_read HI, set on op2_i and issue
  45         m.d.sync += src2_l.s.eq(self.issue_i & self.src2_i)
  46         m.d.sync += src2_l.r.eq(self.go_read_i)
  47
  48         # FU "Forward Progress" (read out horizontally)
  49         m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
  50         m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
  51         m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
  52
  53         # Register File Select (read out vertically)
  54         m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
  55         m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
  56         m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
  57
  58         return m
  59
  60     def __iter__(self):
  61         yield self.dest_i
  62         yield self.src1_i
  63         yield self.src2_i
  64         yield self.issue_i
  65         yield self.go_write_i
  66         yield self.go_read_i
  67         yield self.dest_rsel_o
  68         yield self.src1_rsel_o
  69         yield self.src2_rsel_o
  70         yield self.dest_fwd_o
  71         yield self.src1_fwd_o
  72         yield self.src2_fwd_o
  73
  74     def ports(self):
  75         return list(self)
  76
  77
  78 def dcell_sim(dut):
  79     yield dut.dest_i.eq(1)
  80     yield dut.issue_i.eq(1)
  81     yield
  82     yield dut.issue_i.eq(0)
  83     yield
  84     yield dut.src1_i.eq(1)
  85     yield dut.issue_i.eq(1)
  86     yield
  87     yield dut.issue_i.eq(0)
  88     yield
  89     yield dut.go_read_i.eq(1)
  90     yield
  91     yield dut.go_read_i.eq(0)
  92     yield
  93     yield dut.go_write_i.eq(1)
  94     yield
  95     yield dut.go_write_i.eq(0)
  96     yield
  97
  98 def test_dcell():
  99     dut = DependenceCell()
 100     vl = rtlil.convert(dut, ports=dut.ports())
 101     with open("test_dcell.il", "w") as f:
 102         f.write(vl)
 103
 104     run_simulation(dut, dcell_sim(dut), vcd_name='test_dcell.vcd')
 105
 106 if __name__ == '__main__':
 107     test_dcell()