src/scoreboard/issue_unit.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Array, Const, Record, Elaboratable
   4 from nmutil.latch import SRLatch
   5 from nmigen.lib.coding import Decoder
   6
   7 from shadow_fn import ShadowFn
   8
   9
  10 class IssueUnit(Elaboratable):
  11     """ implements 11.4.14 issue unit, p50
  12
  13         Inputs
  14
  15         * :wid:         register file width
  16         * :n_insns:     number of instructions in this issue unit.
  17     """
  18     def __init__(self, wid, n_insns):
  19         self.reg_width = wid
  20         self.n_insns = n_insns
  21
  22         # inputs
  23         self.store_i = Signal(reset_less=True) # instruction is a store
  24         self.dest_i = Signal(max=wid, reset_less=True) # Dest R# in
  25         self.src1_i = Signal(max=wid, reset_less=True) # oper1 R# in
  26         self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in
  27
  28         self.g_wr_pend_i = Signal(wid, reset_less=True) # write pending vector
  29
  30         self.insn_i = Array(Signal(reset_less=True, name="insn_i") \
  31                                for i in range(n_insns))
  32         self.busy_i = Array(Signal(reset_less=True, name="busy_i") \
  33                                for i in range(n_insns))
  34
  35         # outputs
  36         self.fn_issue_o = Array(Signal(reset_less=True, name="fn_issue_o") \
  37                                for i in range(n_insns))
  38         self.g_issue_o = Signal(reset_less=True)
  39
  40     def elaborate(self, platform):
  41         m = Module()
  42         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
  43
  44         # temporaries
  45         waw_stall = Signal(reset_less=True)
  46         fu_stall = Signal(reset_less=True)
  47         pend = Signal(self.reg_width, reset_less=True)
  48
  49         # dest decoder: write-pending
  50         m.d.comb += dest_d.i.eq(self.dest_i)
  51         m.d.comb += dest_d.n.eq(~self.store_i) # decode is inverted
  52         m.d.comb += pend.eq(dest_d.o & self.g_wr_pend_i)
  53         m.d.comb += waw_stall.eq(pend.bool())
  54
  55         ib_l = []
  56         for i in range(self.n_insns):
  57             ib_l.append(self.insn_i[i] & self.busy_i[i])
  58         m.d.comb += fu_stall.eq(Cat(*ib_l).bool())
  59         m.d.comb += self.g_issue_o.eq(~(waw_stall | fu_stall))
  60         for i in range(self.n_insns):
  61             m.d.comb += self.fn_issue_o[i].eq(self.g_issue_o & self.insn_i[i])
  62
  63         return m
  64
  65     def __iter__(self):
  66         yield self.store_i
  67         yield self.dest_i
  68         yield self.src1_i
  69         yield self.src2_i
  70         yield self.g_wr_pend_i
  71         yield from self.insn_i
  72         yield from self.busy_i
  73         yield from self.fn_issue_o
  74         yield self.g_issue_o
  75
  76     def ports(self):
  77         return list(self)
  78
  79
  80 class IntFPIssueUnit(Elaboratable):
  81     def __init__(self, wid, n_int_insns, n_fp_insns):
  82         self.i = IssueUnit(wid, n_int_insns)
  83         self.f = IssueUnit(wid, n_fp_insns)
  84         self.issue_o = Signal(reset_less=True)
  85
  86         # some renames
  87         self.int_write_pending_i = self.i.g_wr_pend_i
  88         self.fp_write_pending_i = self.f.g_wr_pend_i
  89         self.int_write_pending_i.name = 'int_write_pending_i'
  90         self.fp_write_pending_i.name = 'fp_write_pending_i'
  91
  92     def elaborate(self, platform):
  93         m = Module()
  94         m.submodules.intissue = self.i
  95         m.submodules.fpissue = self.f
  96
  97         m.d.comb += self.issue_o.eq(self.i.g_issue_o | self.f.g_issue_o)
  98
  99         return m
 100
 101     def ports(self):
 102         yield self.issue_o
 103         yield from self.i
 104         yield from self.f
 105
 106
 107 def issue_unit_sim(dut):
 108     yield dut.dest_i.eq(1)
 109     yield dut.issue_i.eq(1)
 110     yield
 111     yield dut.issue_i.eq(0)
 112     yield
 113     yield dut.src1_i.eq(1)
 114     yield dut.issue_i.eq(1)
 115     yield
 116     yield
 117     yield
 118     yield dut.issue_i.eq(0)
 119     yield
 120     yield dut.go_read_i.eq(1)
 121     yield
 122     yield dut.go_read_i.eq(0)
 123     yield
 124     yield dut.go_write_i.eq(1)
 125     yield
 126     yield dut.go_write_i.eq(0)
 127     yield
 128
 129 def test_issue_unit():
 130     dut = IssueUnit(32, 3)
 131     vl = rtlil.convert(dut, ports=dut.ports())
 132     with open("test_issue_unit.il", "w") as f:
 133         f.write(vl)
 134
 135     dut = IntFPIssueUnit(32, 3, 3)
 136     vl = rtlil.convert(dut, ports=dut.ports())
 137     with open("test_intfp_issue_unit.il", "w") as f:
 138         f.write(vl)
 139
 140     run_simulation(dut, issue_unit_sim(dut), vcd_name='test_issue_unit.vcd')
 141
 142 if __name__ == '__main__':
 143     test_issue_unit()