src/scoreboard/ldst_dep_cell.py

   1 """ Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
   2
   3 Relevant bugreports:
   4 * http://bugs.libre-riscv.org/show_bug.cgi?id=81
   5
   6 """
   7
   8 from nmigen.compat.sim import run_simulation
   9 from nmigen.cli import verilog, rtlil
  10 from nmigen import Module, Signal, Elaboratable
  11 from nmutil.latch import SRLatch
  12
  13
  14 class LDSTDepCell(Elaboratable):
  15     """ implements 11.4.12 mitch alsup load/store dependence cell, p45
  16     """
  17     def __init__(self):
  18         # inputs
  19         self.load_i = Signal(reset_less=True)     # load pending in (top)
  20         self.stor_i = Signal(reset_less=True)     # store pending in (top)
  21         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  22
  23         self.load_hit_i = Signal(reset_less=True) # load hit in (right)
  24         self.stwd_hit_i = Signal(reset_less=True) # store w/ data hit in (right)
  25
  26         # outputs (latched rd/wr pend)
  27         self.ld_hold_st_o = Signal(reset_less=True) # load holds st out (left)
  28         self.st_hold_ld_o = Signal(reset_less=True) # st holds load out (left)
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch
  33         m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch
  34
  35         # issue & store & load - used for both WAR and RAW Setting
  36         i_s_l = Signal(reset_less=True)
  37         m.d.comb += i_s_l.eq(self.issue_i & self.stor_i & self.load_i)
  38
  39         # write after read latch: loads block stores
  40         m.d.comb += war_l.s.eq(i_s_l)
  41         m.d.comb += war_l.r.eq(self.load_i) # reset on LD
  42
  43         # read after write latch: stores block loads
  44         m.d.comb += raw_l.s.eq(i_s_l)
  45         m.d.comb += raw_l.r.eq(self.stor_i) # reset on ST
  46
  47         # Hold results (read out horizontally, accumulate in OR fashion)
  48         m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
  49         m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
  50
  51         return m
  52
  53     def __iter__(self):
  54         yield self.load_i
  55         yield self.stor_i
  56         yield self.issue_i
  57         yield self.load_hit_i
  58         yield self.stwd_hit_i
  59         yield self.ld_hold_st_o
  60         yield self.st_hold_ld_o
  61
  62     def ports(self):
  63         return list(self)
  64
  65
  66 def dcell_sim(dut):
  67     yield dut.dest_i.eq(1)
  68     yield dut.issue_i.eq(1)
  69     yield
  70     yield dut.issue_i.eq(0)
  71     yield
  72     yield dut.src1_i.eq(1)
  73     yield dut.issue_i.eq(1)
  74     yield
  75     yield dut.issue_i.eq(0)
  76     yield
  77     yield dut.go_read_i.eq(1)
  78     yield
  79     yield dut.go_read_i.eq(0)
  80     yield
  81     yield dut.go_write_i.eq(1)
  82     yield
  83     yield dut.go_write_i.eq(0)
  84     yield
  85
  86 def test_dcell():
  87     dut = LDSTDepCell()
  88     vl = rtlil.convert(dut, ports=dut.ports())
  89     with open("test_ldst_dcell.il", "w") as f:
  90         f.write(vl)
  91
  92     run_simulation(dut, dcell_sim(dut), vcd_name='test_ldst_dcell.vcd')
  93
  94 if __name__ == '__main__':
  95     test_dcell()