add function unit read/write pending
[ieee754fpu.git] / src / scoreboard / reg_select.py
1 from nmigen import Elaboratable, Module, Signal
2
3
4 class RegReservation(Elaboratable):
5 def __init__(self, fu_count):
6 self.fu_count = fu_count
7 self.dest_rsel_i = Signal(fu_count, reset_less=True)
8 self.src1_rsel_i = Signal(fu_count, reset_less=True)
9 self.src2_rsel_i = Signal(fu_count, reset_less=True)
10 self.dest_rsel_o = Signal(reset_less=True)
11 self.src1_rsel_o = Signal(reset_less=True)
12 self.src2_rsel_o = Signal(reset_less=True)
13
14 def elaboratable(self, platform):
15 m = Module()
16 m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
17 m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())
18 m.d.comb += self.src2_rsel_o.eq(self.src2_rsel_i.bool())
19 return m
20