add regfile selection
[ieee754fpu.git] / src / scoreboard / reg_select.py
1 from nmigen import Elaboratable, Module, Array, Signal
2
3 class RegReservation(Elaboratable):
4 def __init__(self, fu_count):
5 self.fu_count = fu_count
6 self.dest_rsel_i = Signal(fu_count, reset_less=True)
7 self.src1_rsel_i = Signal(fu_count, reset_less=True)
8 self.src2_rsel_i = Signal(fu_count, reset_less=True)
9 self.dest_rsel_o = Signal(reset_less=True)
10 self.src1_rsel_o = Signal(reset_less=True)
11 self.src2_rsel_o = Signal(reset_less=True)
12
13 def elaboratable(self, platform):
14 m = Module()
15 m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
16 m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())
17 m.d.comb += self.src2_rsel_o.eq(self.src2_rsel_i.bool())
18 return m
19