remove extra arg from old roundz function

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 0629ffb5f539defa9c665b0d2a0023e05238abd0..9ed2bf39b9bb67392c602b91484e8b8fdf47ce17 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -1,25 +1,8 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from fpbase import FPNum, FPOp, Overflow, FPBase
-
-class FPState(FPBase):
-    def __init__(self, state_from):
-        self.state_from = state_from
-
-    def set_inputs(self, inputs):
-        self.inputs = inputs
-        for k,v in inputs.items():
-            setattr(self, k, v)
-
-    def set_outputs(self, outputs):
-        self.outputs = outputs
-        for k,v in outputs.items():
-            setattr(self, k, v)
-
-'''
-
-# OLD DESIGN #
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
+from nmigen_add_experiment import FPState
 
 class FPMUL(FPBase):
 
@@ -37,9 +20,9 @@ class FPMUL(FPBase):
         m = Module()
 
         # Latches
-        a = FPNum(self.width, False)
-        b = FPNum(self.width, False)
-        z = FPNum(self.width, False)
+        a = FPNumIn(None, self.width, False)
+        b = FPNumIn(None, self.width, False)
+        z = FPNumOut(self.width, False)
 
         mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
@@ -65,30 +48,30 @@ class FPMUL(FPBase):
 
             with m.State("special_cases"):
                 #if a or b is NaN return NaN
-                with m.If(a.is_nan() | b.is_nan()):
+                with m.If(a.is_nan | b.is_nan):
                     m.next = "put_z"
                     m.d.sync += z.nan(1)
                 #if a is inf return inf
-                with m.Elif(a.is_inf()):
+                with m.Elif(a.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if b is zero return NaN
-                    with m.If(b.is_zero()):
+                    with m.If(b.is_zero):
                         m.d.sync += z.nan(1)
                 #if b is inf return inf
-                with m.Elif(b.is_inf()):
+                with m.Elif(b.is_inf):
                     m.next = "put_z"
                     m.d.sync += z.inf(a.s ^ b.s)
                     #if a is zero return NaN
-                    with m.If(a.is_zero()):
+                    with m.If(a.is_zero):
                         m.next = "put_z"
                         m.d.sync += z.nan(1)
                 #if a is zero return zero
-                with m.Elif(a.is_zero()):
+                with m.Elif(a.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 #if b is zero return zero
-                with m.Elif(b.is_zero()):
+                with m.Elif(b.is_zero):
                     m.next = "put_z"
                     m.d.sync += z.zero(a.s ^ b.s)
                 # Denormalised Number checks
@@ -144,7 +127,8 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of, "corrections")
+                #self.roundz(m, z, of.roundz)
+                m.next = "corrections"
 
             # ******
             # correction stage
@@ -169,5 +153,3 @@ class FPMUL(FPBase):
 if __name__ == "__main__":
     alu = FPMUL(width=32)
     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
-    
-'''