self.m.eq(sm.lshift(self.m, maxslen))
]
-class FPOp:
- def __init__(self, width):
- self.width = width
+class Trigger:
+ def __init__(self):
- self.v = Signal(width)
self.stb = Signal(reset=0)
self.ack = Signal()
self.trigger = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
- m.d.sync += self.trigger.eq(self.stb & self.ack)
+ m.d.comb += self.trigger.eq(self.stb & self.ack)
return m
+ def copy(self, inp):
+ return [self.stb.eq(inp.stb),
+ self.ack.eq(inp.ack)
+ ]
+
+ def ports(self):
+ return [self.stb, self.ack]
+
+
+class FPOp(Trigger):
+ def __init__(self, width):
+ Trigger.__init__(self)
+ self.width = width
+
+ self.v = Signal(width)
+
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
if extra is not None:
with m.Else():
m.next = next_state
- def roundz(self, m, z, out_z, roundz):
+ def roundz(self, m, z, roundz):
""" performs rounding on the output. TODO: different kinds of rounding
"""
- m.d.comb += out_z.copy(z) # copies input to output first
with m.If(roundz):
- m.d.comb += out_z.m.eq(z.m + 1) # mantissa rounds up
+ m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
with m.If(z.m == z.m1s): # all 1s
- m.d.comb += out_z.e.eq(z.e + 1) # exponent rounds up
+ m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
def corrections(self, m, z, next_state):
""" denormalisation and sign-bug corrections