LD/ST latches are async (clockless)

diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py
index ee998e913772fc7fe0c3b5aa9856e18d58906833..f8d6230855b4e798d6ff7e3dae2cd37b382afe73 100644 (file)
--- a/src/scoreboard/ldst_dep_cell.py
+++ b/src/scoreboard/ldst_dep_cell.py
@@ -35,8 +35,8 @@ class LDSTDepCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.war_l = war_l = SRLatch() # Write After Read Latch
-        m.submodules.raw_l = raw_l = SRLatch() # Read After Write Latch
+        m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch
+        m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch
 
         # issue & store & load - used for both WAR and RAW Setting
         i_s_l = Signal(reset_less=True)