use PassThroughStage

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 0795cccd789ce2f2091cf7bdd8b1725dc468637b..819f41f84bdf8b7b7a8edb3be34c707404148cf8 100644 (file)
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -4,6 +4,7 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
+from singlepipe import PassThroughStage
 from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
 
 
@@ -20,16 +21,6 @@ class PassData:
         return [self.mid, self.idx, self.data]
 
 
-class PassThroughStage:
-    def ispec(self):
-        return PassData()
-    def ospec(self):
-        return self.ispec() # same as ospec
-    def process(self, i):
-        return i # pass-through
-
-
-
 def testbench(dut):
     stb = yield dut.out_op.stb
     assert stb == 0
@@ -207,7 +198,8 @@ class InputTest:
 class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self):
         self.num_rows = 4
-        stage = PassThroughStage()
+        def iospecfn(): return PassData()
+        stage = PassThroughStage(iospecfn)
         PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)