mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 728074e9a38f7187bb4e19543685e1146be4c332..29f1bade395031b33a8f09c662f39fe1103cf758 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -20,8 +20,8 @@ class FPMUL(FPBase):
         m = Module()
 
         # Latches
-        a = FPNum(self.width)
-        b = FPNum(self.width)
+        a = FPNum(self.width, False)
+        b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow