self.in_t.ack.eq(self.mod.in_t.ack),
self.o.mid.eq(self.mod.o.mid),
self.o.z.v.eq(self.mod.o.z.v),
- self.o.z.o_valid.eq(self.mod.o.z.o_valid),
- self.mod.o.z.i_ready.eq(self.o.z.i_ready_test),
+ self.o.z.valid_o.eq(self.mod.o.z.valid_o),
+ self.mod.o.z.ready_i.eq(self.o.z.ready_i_test),
]
m.d.sync += self.add_stb.eq(add_stb)
m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
- m.d.sync += self.o.z.i_ready.eq(0) # likewise
+ m.d.sync += self.o.z.ready_i.eq(0) # likewise
#m.d.sync += self.in_t.stb.eq(0)
m.submodules.fpadd = self.mod
with m.Else():
m.d.sync += [self.add_ack.eq(0),
self.in_t.stb.eq(0),
- self.o.z.i_ready.eq(1),
+ self.o.z.ready_i.eq(1),
]
with m.Else():
# done: acknowledge, and write out id and value
m.d.sync += [
out_z.v.eq(z.v)
]
- with m.If(out_z.o_valid & out_z.i_ready_test):
- m.d.sync += out_z.o_valid.eq(0)
+ with m.If(out_z.valid_o & out_z.ready_i_test):
+ m.d.sync += out_z.valid_o.eq(0)
m.next = next_state
with m.Else():
- m.d.sync += out_z.o_valid.eq(1)
+ m.d.sync += out_z.valid_o.eq(1)
class FPState(FPBase):
m.d.sync += [
self.out_z.z.v.eq(self.in_z)
]
- with m.If(self.out_z.z.o_valid & self.out_z.z.i_ready_test):
- m.d.sync += self.out_z.z.o_valid.eq(0)
+ with m.If(self.out_z.z.valid_o & self.out_z.z.ready_i_test):
+ m.d.sync += self.out_z.z.valid_o.eq(0)
m.next = self.to_state
with m.Else():
- m.d.sync += self.out_z.z.o_valid.eq(1)
+ m.d.sync += self.out_z.z.valid_o.eq(1)
class FPPutZIdx(FPState):
def action(self, m):
outz_stb = Signal(reset_less=True)
outz_ack = Signal(reset_less=True)
- m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].o_valid),
- outz_ack.eq(self.out_zs[self.in_mid].i_ready_test),
+ m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].valid_o),
+ outz_ack.eq(self.out_zs[self.in_mid].ready_i_test),
]
m.d.sync += [
self.out_zs[self.in_mid].v.eq(self.in_z.v)
]
with m.If(outz_stb & outz_ack):
- m.d.sync += self.out_zs[self.in_mid].o_valid.eq(0)
+ m.d.sync += self.out_zs[self.in_mid].valid_o.eq(0)
m.next = self.to_state
with m.Else():
- m.d.sync += self.out_zs[self.in_mid].o_valid.eq(1)
+ m.d.sync += self.out_zs[self.in_mid].valid_o.eq(1)
# all outputs to next stages first initialised to zero (invalid)
# the only output "active" is then selected by the muxid
for i in range(len(self.n)):
- m.d.comb += self.n[i].o_valid.eq(0)
- data_valid = self.n[mid].o_valid
- m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].i_ready)
+ m.d.comb += self.n[i].valid_o.eq(0)
+ data_valid = self.n[mid].valid_o
+ m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
m.d.comb += data_valid.eq(p_valid_i | \
- (~self.n[mid].i_ready & data_valid))
+ (~self.n[mid].ready_i & data_valid))
with m.If(pv):
m.d.comb += eq(r_data, self.p.i_data)
m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
r_data = []
data_valid = []
p_valid_i = []
- n_i_readyn = []
+ n_ready_in = []
p_len = len(self.p)
for i in range(p_len):
r = self.stage.ispec() # input type
r_data.append(r)
data_valid.append(Signal(name="data_valid", reset_less=True))
p_valid_i.append(Signal(name="p_valid_i", reset_less=True))
- n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
+ n_ready_in.append(Signal(name="n_ready_in", reset_less=True))
if hasattr(self.stage, "setup"):
self.stage.setup(m, r)
if len(r_data) > 1:
r_data = Array(r_data)
p_valid_i = Array(p_valid_i)
- n_i_readyn = Array(n_i_readyn)
+ n_ready_in = Array(n_ready_in)
data_valid = Array(data_valid)
nirn = Signal(reset_less=True)
- m.d.comb += nirn.eq(~self.n.i_ready)
+ m.d.comb += nirn.eq(~self.n.ready_i)
mid = self.p_mux.m_id
for i in range(p_len):
m.d.comb += data_valid[i].eq(0)
- m.d.comb += n_i_readyn[i].eq(1)
+ m.d.comb += n_ready_in[i].eq(1)
m.d.comb += p_valid_i[i].eq(0)
m.d.comb += self.p[i].ready_o.eq(0)
m.d.comb += p_valid_i[mid].eq(self.p_mux.active)
- m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.i_ready)
- m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
+ m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.ready_i)
+ m.d.comb += n_ready_in[mid].eq(nirn & data_valid[mid])
anyvalid = Signal(i, reset_less=True)
av = []
for i in range(p_len):
av.append(data_valid[i])
anyvalid = Cat(*av)
- m.d.comb += self.n.o_valid.eq(anyvalid.bool())
+ m.d.comb += self.n.valid_o.eq(anyvalid.bool())
m.d.comb += data_valid[mid].eq(p_valid_i[mid] | \
- (n_i_readyn[mid] & data_valid[mid]))
+ (n_ready_in[mid] & data_valid[mid]))
for i in range(p_len):
vr = Signal(reset_less=True)
p_valid_i = self.we
enq_data = self.din
- n_o_valid = self.readable
- n_i_ready = self.re
+ n_valid_o = self.readable
+ n_ready_i = self.re
deq_data = self.dout
# intermediaries
empty.eq(ptr_match & ~maybe_full),
full.eq(ptr_match & maybe_full),
do_enq.eq(p_ready_o & p_valid_i), # write conditions ok
- do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
+ do_deq.eq(n_ready_i & n_valid_o), # read conditions ok
# set readable and writable (NOTE: see pipe mode below)
- n_o_valid.eq(~empty), # cannot read if empty!
+ n_valid_o.eq(~empty), # cannot read if empty!
p_ready_o.eq(~full), # cannot write if full!
# set up memory and connect to input and output
# as Memory "write-through"... without relying on a changing API
if self.fwft:
with m.If(p_valid_i):
- m.d.comb += n_o_valid.eq(1)
+ m.d.comb += n_valid_o.eq(1)
with m.If(empty):
m.d.comb += deq_data.eq(enq_data)
m.d.comb += do_deq.eq(0)
- with m.If(n_i_ready):
+ with m.If(n_ready_i):
m.d.comb += do_enq.eq(0)
# pipe mode: if next stage says it's ready (readable), we
# *must* declare the input ready (writeable).
if self.pipe:
- with m.If(n_i_ready):
+ with m.If(n_ready_i):
m.d.comb += p_ready_o.eq(1)
# set the count (available free space), optimise on power-of-two
* outgoing previous-stage ready (p.ready_o) is LOW
output transmission conditions are when:
- * outgoing next-stage strobe (n.o_valid) is HIGH
- * outgoing next-stage ready (n.i_ready) is LOW
+ * outgoing next-stage strobe (n.valid_o) is HIGH
+ * outgoing next-stage ready (n.ready_i) is LOW
the tricky bit is when the input has valid data and the output is not
ready to accept it. if it wasn't for the clock synchronisation, it
class NextControl(Elaboratable):
""" contains the signals that go *to* the next stage (both in and out)
- * o_valid: output indicating to next stage that data is valid
- * i_ready: input from next stage indicating that it can accept data
+ * valid_o: output indicating to next stage that data is valid
+ * ready_i: input from next stage indicating that it can accept data
* o_data : an output - added by the user of this class
"""
def __init__(self, stage_ctl=False):
self.stage_ctl = stage_ctl
- self.o_valid = Signal(name="n_o_valid") # self out>> next
- self.i_ready = Signal(name="n_i_ready") # self <<in next
+ self.valid_o = Signal(name="n_valid_o") # self out>> next
+ self.ready_i = Signal(name="n_ready_i") # self <<in next
self.o_data = None # XXX MUST BE ADDED BY USER
#if self.stage_ctl:
self.d_valid = Signal(reset=1) # INTERNAL (data valid)
self.trigger = Signal(reset_less=True)
@property
- def i_ready_test(self):
+ def ready_i_test(self):
if self.stage_ctl:
- return self.i_ready & self.d_valid
- return self.i_ready
+ return self.ready_i & self.d_valid
+ return self.ready_i
def connect_to_next(self, nxt):
""" helper function to connect to the next stage data/valid/ready.
data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
use this when connecting stage-to-stage
"""
- return [nxt.valid_i.eq(self.o_valid),
- self.i_ready.eq(nxt.ready_o),
+ return [nxt.valid_i.eq(self.valid_o),
+ self.ready_i.eq(nxt.ready_o),
eq(nxt.i_data, self.o_data),
]
""" internal helper function to connect stage to an output source.
do not use to connect stage-to-stage!
"""
- i_ready = nxt.i_ready if direct else nxt.i_ready_test
+ ready_i = nxt.ready_i if direct else nxt.ready_i_test
o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
- return [nxt.o_valid.eq(self.o_valid),
- self.i_ready.eq(i_ready),
+ return [nxt.valid_o.eq(self.valid_o),
+ self.ready_i.eq(ready_i),
eq(o_data, self.o_data),
]
def elaborate(self, platform):
m = Module()
- m.d.comb += self.trigger.eq(self.i_ready_test & self.o_valid)
+ m.d.comb += self.trigger.eq(self.ready_i_test & self.valid_o)
return m
def __iter__(self):
- yield self.i_ready
- yield self.o_valid
+ yield self.ready_i
+ yield self.valid_o
if hasattr(self.o_data, "ports"):
yield from self.o_data.ports()
elif isinstance(self.o_data, Sequence):
m.d.comb += self.p.s_ready_o.eq(self.p._ready_o & self.stage.d_ready)
# intercept the next (incoming) "ready" and combine it with data valid
- sdv = self.stage.d_valid(self.n.i_ready)
- m.d.comb += self.n.d_valid.eq(self.n.i_ready & sdv)
+ sdv = self.stage.d_valid(self.n.ready_i)
+ m.d.comb += self.n.d_valid.eq(self.n.ready_i & sdv)
return m
Argument: stage. see Stage API above
- stage-1 p.valid_i >>in stage n.o_valid out>> stage+1
- stage-1 p.ready_o <<out stage n.i_ready <<in stage+1
+ stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
+ stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.i_data >>in stage n.o_data out>> stage+1
| |
process --->----^
# establish some combinatorial temporaries
o_n_validn = Signal(reset_less=True)
- n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
+ n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
nir_por = Signal(reset_less=True)
nir_por_n = Signal(reset_less=True)
p_valid_i = Signal(reset_less=True)
por_pivn = Signal(reset_less=True)
npnn = Signal(reset_less=True)
self.m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
- o_n_validn.eq(~self.n.o_valid),
- n_i_ready.eq(self.n.i_ready_test),
- nir_por.eq(n_i_ready & self.p._ready_o),
- nir_por_n.eq(n_i_ready & ~self.p._ready_o),
- nir_novn.eq(n_i_ready | o_n_validn),
- nirn_novn.eq(~n_i_ready & o_n_validn),
+ o_n_validn.eq(~self.n.valid_o),
+ n_ready_i.eq(self.n.ready_i_test),
+ nir_por.eq(n_ready_i & self.p._ready_o),
+ nir_por_n.eq(n_ready_i & ~self.p._ready_o),
+ nir_novn.eq(n_ready_i | o_n_validn),
+ nirn_novn.eq(~n_ready_i & o_n_validn),
npnn.eq(nir_por | nirn_novn),
por_pivn.eq(self.p._ready_o & ~p_valid_i)
]
# data pass-through conditions
with self.m.If(npnn):
o_data = self._postprocess(result)
- self.m.d.sync += [self.n.o_valid.eq(p_valid_i), # valid if p_valid
+ self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
eq(self.n.o_data, o_data), # update output
]
# buffer flush conditions (NOTE: can override data passthru conditions)
with self.m.If(nir_por_n): # not stalled
# Flush the [already processed] buffer to the output port.
o_data = self._postprocess(r_data)
- self.m.d.sync += [self.n.o_valid.eq(1), # reg empty
+ self.m.d.sync += [self.n.valid_o.eq(1), # reg empty
eq(self.n.o_data, o_data), # flush buffer
]
# output ready conditions
Argument: stage. see Stage API above
- stage-1 p.valid_i >>in stage n.o_valid out>> stage+1
- stage-1 p.ready_o <<out stage n.i_ready <<in stage+1
+ stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
+ stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.i_data >>in stage n.o_data out>> stage+1
| |
+--process->--^
result = _spec(self.stage.ospec, "r_tmp")
# establish some combinatorial temporaries
- n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
+ n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
p_valid_i_p_ready_o = Signal(reset_less=True)
p_valid_i = Signal(reset_less=True)
m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
- n_i_ready.eq(self.n.i_ready_test),
+ n_ready_i.eq(self.n.ready_i_test),
p_valid_i_p_ready_o.eq(p_valid_i & self.p.ready_o),
]
eq(self.n.o_data, o_data), # update output
]
# previous invalid or not ready, however next is accepting
- with m.Elif(n_i_ready):
+ with m.Elif(n_ready_i):
o_data = self._postprocess(result)
m.d.sync += [eq(self.n.o_data, o_data)]
# TODO: could still send data here (if there was any)
- #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
+ #m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
m.d.sync += r_busy.eq(0) # ...so set output invalid
- m.d.comb += self.n.o_valid.eq(r_busy)
+ m.d.comb += self.n.valid_o.eq(r_busy)
# if next is ready, so is previous
- m.d.comb += self.p._ready_o.eq(n_i_ready)
+ m.d.comb += self.p._ready_o.eq(n_ready_i)
return self.m
Argument: stage. see Stage API, above
- stage-1 p.valid_i >>in stage n.o_valid out>> stage+1
- stage-1 p.ready_o <<out stage n.i_ready <<in stage+1
+ stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
+ stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.i_data >>in stage n.o_data out>> stage+1
| |
r_data result
buf_full = Signal(reset_less=True)
m.d.comb += p_valid_i.eq(self.p.valid_i_test)
m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
- m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
+ m.d.comb += buf_full.eq(~self.n.ready_i_test & data_valid)
- m.d.comb += self.n.o_valid.eq(data_valid)
- m.d.comb += self.p._ready_o.eq(~data_valid | self.n.i_ready_test)
+ m.d.comb += self.n.valid_o.eq(data_valid)
+ m.d.comb += self.p._ready_o.eq(~data_valid | self.n.ready_i_test)
m.d.sync += data_valid.eq(p_valid_i | buf_full)
with m.If(pv):
Argument: stage. see Stage API, above
- stage-1 p.valid_i >>in stage n.o_valid out>> stage+1
- stage-1 p.ready_o <<out stage n.i_ready <<in stage+1
+ stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
+ stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.i_data >>in stage n.o_data out>> stage+1
| | |
+- process-> buf <-+
p_valid_i = Signal(reset_less=True)
m.d.comb += p_valid_i.eq(self.p.valid_i_test)
- m.d.comb += self.n.o_valid.eq(buf_full | p_valid_i)
+ m.d.comb += self.n.valid_o.eq(buf_full | p_valid_i)
m.d.comb += self.p._ready_o.eq(~buf_full)
- m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
+ m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
o_data = self._postprocess(o_data)
m.d.comb += p_valid_i.eq(self.p.valid_i_test)
m.d.comb += pvr.eq(p_valid_i & self.p.ready_o)
- m.d.comb += self.p.ready_o.eq(~self.n.o_valid | self.n.i_ready_test)
- m.d.sync += self.n.o_valid.eq(p_valid_i | ~self.p.ready_o)
+ m.d.comb += self.p.ready_o.eq(~self.n.valid_o | self.n.ready_i_test)
+ m.d.sync += self.n.valid_o.eq(p_valid_i | ~self.p.ready_o)
odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
m.d.sync += eq(r_data, odata)
class RegisterPipeline(UnbufferedPipeline):
""" A pipeline stage that delays by one clock cycle, creating a
- sync'd latch out of o_data and o_valid as an indirect byproduct
+ sync'd latch out of o_data and valid_o as an indirect byproduct
of using PassThroughStage
"""
def __init__(self, iospecfn):
]
# connect next rdy/valid/data - do cat on o_data
- connections = [self.n.o_valid.eq(fifo.readable),
- fifo.re.eq(self.n.i_ready_test),
+ connections = [self.n.valid_o.eq(fifo.readable),
+ fifo.re.eq(self.n.ready_i_test),
]
if self.fwft or self.buffered:
m.d.comb += connections
def check_o_n_valid(dut, val):
- o_n_valid = yield dut.n.o_valid
+ o_n_valid = yield dut.n.valid_o
assert o_n_valid == val
def check_o_n_valid2(dut, val):
- o_n_valid = yield dut.n.o_valid
+ o_n_valid = yield dut.n.valid_o
assert o_n_valid == val
def tbench(dut):
#yield dut.i_p_rst.eq(1)
- yield dut.n.i_ready.eq(0)
+ yield dut.n.ready_i.eq(0)
#yield dut.p.ready_o.eq(0)
yield
yield
#yield dut.i_p_rst.eq(0)
- yield dut.n.i_ready.eq(1)
+ yield dut.n.ready_i.eq(1)
yield dut.p.i_data.eq(5)
yield dut.p.valid_i.eq(1)
yield
yield dut.p.i_data.eq(2)
yield
- yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
yield dut.p.i_data.eq(9)
yield
yield dut.p.valid_i.eq(0)
yield dut.p.i_data.eq(12)
yield
yield dut.p.i_data.eq(32)
- yield dut.n.i_ready.eq(1)
+ yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield
def tbench2(dut):
#yield dut.p.i_rst.eq(1)
- yield dut.n.i_ready.eq(0)
+ yield dut.n.ready_i.eq(0)
#yield dut.p.ready_o.eq(0)
yield
yield
#yield dut.p.i_rst.eq(0)
- yield dut.n.i_ready.eq(1)
+ yield dut.n.ready_i.eq(1)
yield dut.p.i_data.eq(5)
yield dut.p.valid_i.eq(1)
yield
yield dut.p.i_data.eq(2)
yield
yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
yield dut.p.i_data.eq(9)
yield
yield dut.p.valid_i.eq(0)
yield dut.p.i_data.eq(12)
yield
yield dut.p.i_data.eq(32)
- yield dut.n.i_ready.eq(1)
+ yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid2(dut, 1) # buffer still needs to output
yield
stall_range = randint(0, 3)
for j in range(randint(1,10)):
stall = randint(0, stall_range) != 0
- yield self.dut.n.i_ready.eq(stall)
+ yield self.dut.n.ready_i.eq(stall)
yield
- o_n_valid = yield self.dut.n.o_valid
- i_n_ready = yield self.dut.n.i_ready_test
+ o_n_valid = yield self.dut.n.valid_o
+ i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
o_data = yield self.dut.n.o_data
for j in range(randint(1,10)):
ready = randint(0, stall_range) != 0
#ready = True
- yield self.dut.n.i_ready.eq(ready)
+ yield self.dut.n.ready_i.eq(ready)
yield
- o_n_valid = yield self.dut.n.o_valid
- i_n_ready = yield self.dut.n.i_ready_test
+ o_n_valid = yield self.dut.n.valid_o
+ i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
if isinstance(self.dut.n.o_data, Record):
while True:
stall = randint(0, 3) != 0
send = randint(0, 5) != 0
- yield dut.n.i_ready.eq(stall)
+ yield dut.n.ready_i.eq(stall)
o_p_ready = yield dut.p.ready_o
if o_p_ready:
if send and i != len(data):
else:
yield dut.p.valid_i.eq(0)
yield
- o_n_valid = yield dut.n.o_valid
- i_n_ready = yield dut.n.i_ready_test
+ o_n_valid = yield dut.n.valid_o
+ i_n_ready = yield dut.n.ready_i_test
if o_n_valid and i_n_ready:
o_data = yield dut.n.o_data
assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
return (self.count == 1)# | (self.count == 3)
return Const(1)
- def d_valid(self, i_ready):
+ def d_valid(self, ready_i):
""" data is valid at output when this is true
"""
return self.count == self.valid_trigger
print ("test 2")
dut = ExampleBufPipe2()
run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe2.il", "w") as f:
test = Test5(dut, resultfn_6)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
list(dut.p.i_data) + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_ltcomb_pipe.il", "w") as f:
dut = ExampleAddRecordPipe()
data=data_dict()
test = Test5(dut, resultfn_7, data=data)
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o,
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o,
dut.p.i_data.src1, dut.p.i_data.src2,
dut.n.o_data.src1, dut.n.o_data.src2]
vl = rtlil.convert(dut, ports=ports)
print ("test 9")
dut = ExampleBufPipeChain2()
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipechain2.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe12.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe13.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf15.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf16.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe17.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_passthru18.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass19.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifo20.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifopass21.il", "w") as f:
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data.op1, dut.p.i_data.op2] + \
[dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data.op1, dut.p.i_data.op2] + \
[dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
dut = FIFOTestRecordAddStageControl()
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data.op1, dut.p.i_data.op2] + \
[dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_add2pipe25.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass997.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe14.il", "w") as f:
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
- ports = [dut.p.valid_i, dut.n.i_ready,
- dut.n.o_valid, dut.p.ready_o] + \
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf999.il", "w") as f:
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
- # yield self.dut.n[0].i_ready.eq(stall)
+ # yield self.dut.n[0].ready_i.eq(stall)
# yield
n = self.dut.n[mid]
- yield n.i_ready.eq(1)
+ yield n.ready_i.eq(1)
yield
- o_n_valid = yield n.o_valid
- i_n_ready = yield n.i_ready
+ o_n_valid = yield n.valid_o
+ i_n_ready = yield n.ready_i
if not o_n_valid or not i_n_ready:
continue
m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
- m.d.comb += self.n.o_valid.eq(self.fpdiv.out_z.o_valid)
- m.d.comb += self.fpdiv.out_z.i_ready.eq(self.n.i_ready_test)
+ m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
+ m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
m.d.comb += self.n.o_data.eq(self.fpdiv.out_z.v)
return m
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
- # yield self.dut.n[0].i_ready.eq(stall)
+ # yield self.dut.n[0].ready_i.eq(stall)
# yield
n = self.dut.n[mid]
- yield n.i_ready.eq(1)
+ yield n.ready_i.eq(1)
yield
- o_n_valid = yield n.o_valid
- i_n_ready = yield n.i_ready
+ o_n_valid = yield n.valid_o
+ i_n_ready = yield n.ready_i
if not o_n_valid or not i_n_ready:
continue
count += 1
assert count != 2000, "timeout: too long"
n = self.dut.n[mid]
- yield n.i_ready.eq(1)
+ yield n.ready_i.eq(1)
yield
- o_n_valid = yield n.o_valid
- i_n_ready = yield n.i_ready
+ o_n_valid = yield n.valid_o
+ i_n_ready = yield n.ready_i
if not o_n_valid or not i_n_ready:
continue
stall_range = randint(0, 3)
stall = randint(0, stall_range) != 0
if stall:
- yield n.i_ready.eq(0)
+ yield n.ready_i.eq(0)
for i in range(stall_range):
yield
res = [self.p.valid_i, self.p.ready_o] + \
self.p.i_data.ports()
for i in range(len(self.n)):
- res += [self.n[i].i_ready, self.n[i].o_valid] + \
+ res += [self.n[i].ready_i, self.n[i].valid_o] + \
[self.n[i].o_data]
#self.n[i].o_data.ports()
return res
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
- # yield self.dut.n[0].i_ready.eq(stall)
+ # yield self.dut.n[0].ready_i.eq(stall)
# yield
n = self.dut.n
- yield n.i_ready.eq(1)
+ yield n.ready_i.eq(1)
yield
- o_n_valid = yield n.o_valid
- i_n_ready = yield n.i_ready
+ o_n_valid = yield n.valid_o
+ i_n_ready = yield n.ready_i
if not o_n_valid or not i_n_ready:
continue
yield in_b.valid_i.eq(0)
- yield out_z.i_ready.eq(1)
+ yield out_z.ready_i.eq(1)
while True:
- out_z_stb = (yield out_z.o_valid)
+ out_z_stb = (yield out_z.valid_o)
if not out_z_stb:
yield
continue
vout_z = yield out_z.v
#out_mid = yield dut.ids.out_mid
- yield out_z.i_ready.eq(0)
+ yield out_z.ready_i.eq(0)
yield
break
yield dut.in_b.valid_i.eq(0)
- yield dut.out_z.i_ready.eq(1)
+ yield dut.out_z.ready_i.eq(1)
while True:
- out_z_stb = (yield dut.out_z.o_valid)
+ out_z_stb = (yield dut.out_z.valid_o)
if not out_z_stb:
yield
continue
out_z = yield dut.out_z.v
#out_mid = yield dut.out_mid
- yield dut.out_z.i_ready.eq(0)
+ yield dut.out_z.ready_i.eq(0)
yield
break
projects / ieee754fpu.git / commitdiff