fix test_fpmul_pipe_32.py after new PipelineSpec class added

diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index 27f677c7a2056f72bc67c914454f3df0e10b0c9b..fb7f3b26998679b624b5a03c255a0b063ce2e4d0 100644 (file)
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -91,10 +91,10 @@ class FPPipeContext:
                                    "operator". instance must have an "eq"
                                    function.
         """
-        self.id_wid = pspec.id_width
-        self.op_wid = pspec.get('op_wid', 0)
+        self.id_wid = pspec.id_wid
+        self.op_wid = pspec.op_wid
         self.muxid = Signal(self.id_wid, reset_less=True)   # RS multiplex ID
-        opkls = pspec.get('opkls', None)
+        opkls = pspec.opkls
         if opkls is None:
             self.op = Signal(self.op_wid, reset_less=True)
         else:

diff --git a/src/ieee754/pipeline.py b/src/ieee754/pipeline.py
index f2ec693379abb71dc8e83e03770440e4800564dd..c7446337981058e35a7f5289bded82281a151c57 100644 (file)
--- a/src/ieee754/pipeline.py
+++ b/src/ieee754/pipeline.py
@@ -6,12 +6,13 @@ class PipelineSpec:
     """ Pipeline Specification base class.
 
     :attribute width: FIXME: document
-    :attribute id_width: FIXME: document
-    :attribute opcode_width: FIXME: document
+    :attribute id_wid: FIXME: document
+    :attribute op_wid: FIXME: document
     """
 
     def __init__(self, width, id_width, opcode_width):
         """ Create a PipelineSpec. """
         self.width = width
-        self.id_width = id_width
-        self.opcode_width = opcode_width
+        self.id_wid = id_width
+        self.op_wid = opcode_width
+        self.opkls = None