add an example of a stage that is itself a module

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index e38043ecd7775959e65a15341c83b5636a895748..be472c4311853a189ce8ba154360d6ca867b6cd0 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -342,6 +342,28 @@ class LTStage:
         return self.o
 
 
+class LTStageDerived(SetLessThan):
+
+    def __init__(self):
+        SetLessThan.__init__(self, 16, True)
+
+    def ispec(self):
+        return (Signal(16), Signal(16))
+
+    def ospec(self):
+        return Signal(16)
+
+    def setup(self, m, i):
+        self.o = Signal(16)
+        m.submodules.slt = self
+        m.d.comb += self.src1.eq(i[0])
+        m.d.comb += self.src2.eq(i[1])
+        m.d.comb += self.o.eq(self.output)
+
+    def process(self, i):
+        return self.o
+
+
 class ExampleLTCombPipe(CombPipe):
     """ an example of how to use the combinatorial pipeline.
     """
@@ -351,6 +373,15 @@ class ExampleLTCombPipe(CombPipe):
         CombPipe.__init__(self, stage)
 
 
+class ExampleLTBufferedPipeDerived(CombPipe):
+    """ an example of how to use the combinatorial pipeline.
+    """
+
+    def __init__(self):
+        stage = LTStageDerived()
+        CombPipe.__init__(self, stage)
+
+
 def test6_resultfn(o_data, expected, i, o):
     res = 1 if expected[0] < expected[1] else 0
     assert o_data == res, \
@@ -537,3 +568,8 @@ if __name__ == '__main__':
     run_simulation(dut, [test.send, test.rcv],
                         vcd_name="test_bufpipechain2.vcd")
 
+    print ("test 10")
+    dut = ExampleLTBufferedPipeDerived()
+    test = Test5(dut, test6_resultfn)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltbufpipe10.vcd")
+