minor reorg of latch

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 7c59b98395d733e32478c6a43d1760e912eea07d..dbdb23e55b76e660cec8a2c2b7ec80393147da7f 100644 (file)
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -13,13 +13,14 @@ class SRLatch(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         q_int = Signal(reset_less=True)
-        qn_int = Signal(reset_less=True)
 
-        m.d.comb += self.q.eq(~(self.s | qn_int))
-        m.d.comb += self.qn.eq(~(self.r | q_int))
+        with m.If(self.s):
+            m.d.sync += q_int.eq(1)
+        with m.Elif(self.r):
+            m.d.sync += q_int.eq(0)
 
-        m.d.sync += q_int.eq(self.q)
-        m.d.sync += qn_int.eq(self.qn)
+        m.d.comb += self.q.eq(q_int)
+        m.d.comb += self.qn.eq(~q_int)
 
         return m
 
@@ -31,15 +32,24 @@ def sr_sim(dut):
     yield dut.s.eq(0)
     yield dut.r.eq(0)
     yield
+    yield
+    yield
     yield dut.s.eq(1)
     yield
+    yield
+    yield
     yield dut.s.eq(0)
     yield
+    yield
+    yield
     yield dut.r.eq(1)
     yield
+    yield
+    yield
     yield dut.r.eq(0)
     yield
     yield
+    yield
 
 def test_sr():
     dut = SRLatch()

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 7c2d883dbcb53f36e7b0168cde7fdc7b965c6112..18e8d75556ab0338e3021c81c52d587d01787063 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -34,16 +34,16 @@ class DependenceCell(Elaboratable):
         m.submodules.src2_l = src2_l = SRLatch()
 
         # destination latch: reset on go_write HI, set on dest and issue
-        m.d.sync += dest_l.s.eq(self.issue_i & self.dest_i)
-        m.d.sync += dest_l.r.eq(self.go_write_i)
+        m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
+        m.d.comb += dest_l.r.eq(self.go_write_i)
 
         # src1 latch: reset on go_read HI, set on src1_i and issue
-        m.d.sync += src1_l.s.eq(self.issue_i & self.src1_i)
-        m.d.sync += src1_l.r.eq(self.go_read_i)
+        m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i)
+        m.d.comb += src1_l.r.eq(self.go_read_i)
 
         # src2 latch: reset on go_read HI, set on op2_i and issue
-        m.d.sync += src2_l.s.eq(self.issue_i & self.src2_i)
-        m.d.sync += src2_l.r.eq(self.go_read_i)
+        m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
+        m.d.comb += src2_l.r.eq(self.go_read_i)
 
         # FU "Forward Progress" (read out horizontally)
         m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
@@ -84,6 +84,8 @@ def dcell_sim(dut):
     yield dut.src1_i.eq(1)
     yield dut.issue_i.eq(1)
     yield
+    yield
+    yield
     yield dut.issue_i.eq(0)
     yield
     yield dut.go_read_i.eq(1)

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index a7b6d918a972827bf115ea4898ee13e77a4d42b5..93ef28d3cbd82f609f585225960ce2ed06702169 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -26,12 +26,12 @@ class FUDependenceCell(Elaboratable):
         m.submodules.wr_l = wr_l = SRLatch()
 
         # write latch: reset on go_write HI, set on write pending and issue
-        m.d.sync += wr_l.s.eq(self.issue_i & self.wr_pend_i)
-        m.d.sync += wr_l.r.eq(self.go_write_i)
+        m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
+        m.d.comb += wr_l.r.eq(self.go_write_i)
 
         # read latch: reset on go_read HI, set on read pending and issue
-        m.d.sync += rd_l.s.eq(self.issue_i & self.rd_pend_i)
-        m.d.sync += rd_l.r.eq(self.go_read_i)
+        m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i)
+        m.d.comb += rd_l.r.eq(self.go_read_i)
 
         # Read/Write Pending Latches (read out horizontally)
         m.d.comb += self.wr_pend_o.eq(wr_l.qn)