rename TestHyperRAMPHY to just HyperRAMPHY

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index 626043cd856e1faa2bd86eb2dc9e063023bcd8e9..36c72e9fa824c24df367476aa6472dee4b039bd8 100644 (file)
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -96,7 +96,7 @@ class HyperRAMPads:
         self.rwds = Record([("oe", 1), ("o", dw//8),  ("i", dw//8)])
 
 
-class TestHyperRAMPHY(Elaboratable):
+class HyperRAMPHY(Elaboratable):
     def __init__(self, pads):
         self.pads = pads
         self.clk = pads.clk

diff --git a/lambdasoc/test/test_hyperbus.py b/lambdasoc/test/test_hyperbus.py
index 3526bfc94c179392a7e966f60d52c9eef82ceeb8..41f2c54ee169b81dbc3e8ea39e92d0c649fcfb3b 100644 (file)
--- a/lambdasoc/test/test_hyperbus.py
+++ b/lambdasoc/test/test_hyperbus.py
@@ -13,7 +13,7 @@ import unittest
 from nmigen import (Record, Module, Signal, Elaboratable)
 from nmigen.compat.sim import run_simulation
 
-from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, TestHyperRAMPHY
+from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, HyperRAMPHY
 
 def c2bool(c):
     return {"-": 1, "_": 0}[c]
@@ -95,7 +95,7 @@ class TestHyperBusWrite(unittest.TestCase):
                                     (yield dut.phy.pads.rwds.o))
                 yield
 
-        dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
+        dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
                             vcd_name="sim.vcd")
 
@@ -133,7 +133,7 @@ class TestHyperBusWrite(unittest.TestCase):
                             (yield dut.phy.pads.rwds.oe))
                 yield
 
-        dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
+        dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
                             vcd_name="rd_sim.vcd")
 
@@ -180,7 +180,7 @@ class TestHyperBusRead(unittest.TestCase):
                             (yield dut.phy.pads.rwds.oe))
                 yield
 
-        dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
+        dut = HyperRAM(io=HyperRAMPads(), phy_kls=HyperRAMPHY)
         run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
                             vcd_name="rd_sim.vcd")