examples/sdram_soc: reduce L1 sizes to 1KB to meet timing.

diff --git a/examples/sdram_soc.py b/examples/sdram_soc.py
index bbe68ebc6a5a89c20cfdff04c052d5a03ddc2b2c..d3f5dcbced5642fc2627d2aa010719ec419ba6c0 100644 (file)
--- a/examples/sdram_soc.py
+++ b/examples/sdram_soc.py
@@ -32,9 +32,9 @@ class SDRAMSoC(CPUSoC, Elaboratable):
 
         self.cpu = MinervaCPU(
             reset_address=reset_addr,
-            with_icache=True, icache_nlines=128, icache_nwords=4, icache_nways=1,
+            with_icache=True, icache_nlines=64, icache_nwords=4, icache_nways=1,
                               icache_base=sdram_addr, icache_limit=sdram_addr + sdram_core.size,
-            with_dcache=True, dcache_nlines=128, dcache_nwords=4, dcache_nways=1,
+            with_dcache=True, dcache_nlines=64, dcache_nwords=4, dcache_nways=1,
                               dcache_base=sdram_addr, dcache_limit=sdram_addr + sdram_core.size,
             with_muldiv=True,
         )