minor simplification of hyperram: using constants
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Mar 2022 11:36:06 +0000 (12:36 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Mar 2022 11:36:06 +0000 (12:36 +0100)
in m.If(test) can be done as plain python "if(test)"

lambdasoc/periph/hyperram.py

index 3527ee41e5a3deeea8d703a3775f02d9f67da06c..b8bff738beafc81dc25d939c64c0efd2c14b7166 100644 (file)
@@ -242,8 +242,10 @@ class HyperRAM(Peripheral, Elaboratable):
         # Sequencer -------------------------------------------------------
         cycles = Signal(8)
         first  = Signal()
+        nfirst  = Signal() # not-first
         count_inc = Signal()
         dbg_cyc = Signal(8)
+        comb += nfirst.eq(~first) # convenience
 
         # when not idle run a cycles counter
         with m.If(count_inc):
@@ -300,7 +302,7 @@ class HyperRAM(Peripheral, Elaboratable):
                         sync += cycles.eq(0)
                         # On last state, see if we can continue the burst 
                         # or if we should end it.
-                        with m.If(n == (states - 1)):
+                        if n == states - 1:
                             sync += first.eq(0)
                             # Continue burst when consecutive access ready.
                             with m.If(bus.stb & bus.cyc & 
@@ -310,12 +312,12 @@ class HyperRAM(Peripheral, Elaboratable):
                                 # Early Write Ack (to allow bursting).
                                 comb += bus.ack.eq(bus.we)
                             # Else end the burst.
-                            with m.Elif(bus_we | ~first):
+                            with m.Elif(bus_we | nfirst):
                                 m.next = "IDLE"
                                 sync += cycles.eq(0)
                         # Read Ack (when dat_r ready).
-                        with m.If((n == 0) & ~first):
-                            comb += bus.ack.eq(~bus_we)
+                        if n == 0:
+                            comb += bus.ack.eq(nfirst & ~bus_we)
 
         return m