1 # RFC ls006 FPR <-> GPR Move/Conversion
3 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
4 Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
5 * <https://libre-soc.org/openpower/sv/int_fp_mv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls006.fpintmv/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1015>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/todo>
20 **Books and Section affected**: **UPDATE**
22 * Book I 4.6.5 Floating-Point Move Instructions
23 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
24 * Appendix E Power ISA sorted by opcode
25 * Appendix F Power ISA sorted by version
26 * Appendix G Power ISA sorted by Compliancy Subset
27 * Appendix H Power ISA sorted by mnemonic
31 Single-precision Instructions added:
33 * `mffprs` -- Move From FPR Single
34 * `mtfprs` -- Move To FPR Single
35 * `ctfprs` -- Convert To FPR Single
37 Identical (except Double-precision) Instructions added:
39 * `mffpr` -- Move From FPR
40 * `mtfpr` -- Move To FPR
41 * `cffpr` -- Convert From FPR
42 * `ctfpr` -- Convert To FPR
44 **Submitter**: Luke Leighton (Libre-SOC)
46 **Requester**: Libre-SOC
48 **Impact on processor**:
50 * Addition of three new Single-Precision GPR-FPR-based instructions
51 * Addition of four new Double-Precision GPR-FPR-based instructions
53 **Impact on software**:
55 * Requires support for new instructions in assembler, debuggers,
61 GPR, FPR, Move, Conversion, ECMAScript, Saturating
66 CPUs without VSX/VMX lack a way to efficiently transfer data between
67 FPRs and GPRs, they need to go through memory, this proposal adds more
68 efficient data transfer (both bitwise copy and Integer <-> FP conversion)
69 instructions that transfer directly between FPRs and GPRs without needing
72 IEEE 754 does not specify what results are obtained when converting a NaN
73 or out-of-range floating-point value to integer: consequently, different
75 languages and ISAs have made different choices, making binary portability
76 very difficult. Below is an overview
77 of the different variants, listing the languages and hardware that
78 implements each variant.
80 **Notes and Observations**:
82 * These instructions are present in many other ISAs.
83 * ECMAScript rounding as one instruction saves 32 scalar instructions
84 including seven branch instructions.
85 * Both sets are orthogonal (no difference except being Single/Double).
86 This allows IBM to follow the pre-existing precedent of allocating
87 separate Major Opcodes (PO) for Double-precision and Single-precision
92 Add the following entries to:
94 * Book I 4.6.5 Floating-Point Move Instructions
95 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
96 * Book I 1.6.1 and 1.6.2
102 [[!inline pages="openpower/sv/int_fp_mv/cvt_fp_to_int_overview" raw=yes ]]
108 [[!inline pages="openpower/sv/int_fp_mv/moves_and_conversions" raw=yes ]]
114 # Instruction Formats
116 Add the following entries to Book I 1.6.1.19 XO-FORM:
119 |0 |6 |11 |13 |16 |21 |22 |31 |
120 | PO | RT | IT | CVM | FRB | OE | XO | Rc |
123 Add the following entries to Book I 1.6.1.15 X-FORM:
126 |0 |6 |11 |13 |16 |21 |31 |
127 | PO | FRT | IT | // | RB | XO | Rc |
128 | PO | FRT | // | RB | XO | Rc |
129 | PO | RT | // | FRB | XO | Rc |
134 Add XO to FRB's Formats list in Book I 1.6.2 Word Instruction Fields.
136 Add XO to FRT's Formats list in Book I 1.6.2 Word Instruction Fields.
142 Field used to specify integer type for FPR <-> GPR conversions.
147 Field used to specify conversion mode for
148 integer -> floating-point conversion.
159 Appendix E Power ISA sorted by opcode
160 Appendix F Power ISA sorted by version
161 Appendix G Power ISA sorted by Compliancy Subset
162 Appendix H Power ISA sorted by mnemonic
164 |Form| Book | Page | Version | mnemonic | Description |
165 |----|------|------|---------|----------|-------------|
166 |VA | I | # | 3.2B |todo | |