The key technical challenge in this project is to rework the special Simple-V
instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community.
The key technical challenge in this project is to rework the special Simple-V
instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community.