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author
lkcl
<lkcl@web>
Sat, 17 Feb 2024 23:46:14 +0000
(23:46 +0000)
committer
IkiWiki
<ikiwiki.info>
Sat, 17 Feb 2024 23:46:14 +0000
(23:46 +0000)
nlnet_2023_simplev_riscv_binutils.mdwn
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diff --git
a/nlnet_2023_simplev_riscv_binutils.mdwn
b/nlnet_2023_simplev_riscv_binutils.mdwn
index 0cbeceddb4349933a48178470635995b4bcadbf4..97c8353826af0656856340ff80a079c557e3fc40 100644
(file)
--- a/
nlnet_2023_simplev_riscv_binutils.mdwn
+++ b/
nlnet_2023_simplev_riscv_binutils.mdwn
@@
-20,7
+20,8
@@
Please be short and to the point in your answers; focus primarily on the what an
## Abstract: Can you explain the whole project and its expected outcome(s).
## Abstract: Can you explain the whole project and its expected outcome(s).
-This project is to enhance binutils tools to continue the autogenerated supportfor the
+This project is to enhance binutils tools to continue the autogenerated support
+for the
RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
It will directly support the ISA Expansion project
<https://libre-soc.org/nlnet_2023_simplev_riscv>
RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
It will directly support the ISA Expansion project
<https://libre-soc.org/nlnet_2023_simplev_riscv>
@@
-51,7
+52,7
@@
Key phases of this project are:
and SVP64/Power (currently based on an early iteration of libopid)
* Definition of assembler and disassembler for RISC-V
instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
and SVP64/Power (currently based on an early iteration of libopid)
* Definition of assembler and disassembler for RISC-V
instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
-* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single
+* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Sing
l
e and SVP32Single
and implementation support of the same for both Power and RISC-V
(https://libre-soc.org/openpower/sv/svp64-single/)
* Test vectors for libopid and binutils
and implementation support of the same for both Power and RISC-V
(https://libre-soc.org/openpower/sv/svp64-single/)
* Test vectors for libopid and binutils