2 .
/ls180soc.py
--build
--platform
=ls180sram4k
--num-srams
=2 --srams4k
3 cp build
/ls180sram4k
/gateware
/ls180sram4k.v .
/ls180.v
4 cp build
/ls180sram4k
/gateware
/mem.init .
5 cp build
/ls180sram4k
/gateware
/mem_1.init .
6 cp libresoc
/libresoc.v .
7 cp libresoc
/SPBlock_512W64B8W.v .
8 yosys
-p
'read_verilog libresoc.v' \
9 -p
'write_ilang libresoc_cvt.il'
10 yosys
-p
'read_verilog ls180.v' \
11 -p
'read_verilog SPBlock_512W64B8W.v' \
12 -p
'write_ilang ls180_cvt.il'
13 yosys
-p
'read_ilang ls180_cvt.il' \
14 -p
'read_ilang libresoc_cvt.il' \
15 -p
'write_ilang ls180.il'
18 .
/ls180soc.py
--build
--platform
=ls180
--num-srams
=2
19 cp build
/ls180
/gateware
/ls180.v .
20 cp build
/ls180
/gateware
/mem.init .
21 cp build
/ls180
/gateware
/mem_1.init .
22 cp libresoc
/libresoc.v .
23 cp libresoc
/SPBlock_512W64B8W.v .
24 yosys
-p
'read_verilog libresoc.v' \
25 -p
'read_verilog ls180.v' \
27 -p
'write_verilog ls180_cvt.v'
28 yosys
-p
'read_verilog ls180.v' \
29 -p
'read_verilog SPBlock_512W64B8W.v' \
30 -p
'write_ilang ls180_cvt.il'
31 yosys
-p
'read_verilog libresoc.v' \
32 -p
'write_ilang libresoc_cvt.il'
33 yosys
-p
'read_verilog ls180.v' \
34 -p
'read_verilog SPBlock_512W64B8W.v' \
35 -p
'write_ilang ls180_cvt.il'
36 yosys
-p
'read_ilang ls180_cvt.il' \
37 -p
'read_ilang libresoc_cvt.il' \
38 -p
'write_ilang ls180.il'
41 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--build
44 .
/versa_ecp5.py
--sys-clk-freq
=55e6
--load
47 python3 .
/versa_ecp5.py
--sys-clk-freq
=100e6
--build
--fpga
=artya7100t \