reduce jtag data bus width to 32, to match litex

set (ignored) pc_i to 64 bit
remove mem_2.init cp

diff --git a/Makefile b/Makefile
index bd7734ec5b93f87c497be5954c1de51a7ef19f48..5ea2421f41bf213e7564b0b61c08ef4d7b653b77 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -18,9 +18,6 @@ ls180:
        cp build/ls180/gateware/ls180.v .
        cp build/ls180/gateware/mem.init .
        cp build/ls180/gateware/mem_1.init .
-       cp build/ls180/gateware/mem_2.init .
-       cp build/ls180/gateware/mem_3.init .
-       cp build/ls180/gateware/mem_4.init .
        cp libresoc/libresoc.v .
        yosys -p 'read_verilog libresoc.v' \
              -p 'read_verilog ls180.v' \

diff --git a/libresoc/core.py b/libresoc/core.py
index ebf214e2e89ec7251d48404e99b82dc744130125..8fae4198f7ba4b7e526a4a8c99a3c834b4efc30e 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -206,7 +206,7 @@ class LibreSoC(CPU):
         if "testgpio" in variant:
             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
         if jtag_en:
-            self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
+            self.jtag_wb = jtag_wb = wb.Interface(data_width=32, adr_width=30)
 
         self.srams = srams = []
         if "sram4k" in variant:
@@ -238,7 +238,7 @@ class LibreSoC(CPU):
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging
-            i_pc_i             = 0,
+            i_pc_i             = Signal(64),
             i_pc_i_ok          = 0,
             i_core_bigendian_i = 0, # Signal(),
             o_busy_o           = Signal(),   # not connected