enabled debug printing of MSR

diff --git a/sim.py b/sim.py
index accac4fabc3196f3f39c0c1f3caf396953f69a69..c4d1b9d257fae4ce3bbf70e827816132e6a567d5 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -304,9 +304,9 @@ class LibreSoCSim(SoCSDRAM):
              If(dbg_addr == 0b10, # PC
                  pc.eq(dbg_dout),     # capture PC
              ),
-             #If(dbg_addr == 0b11, # MSR
-             #   Display("    msr: %016x", dbg_dout),
-             #),
+             If(dbg_addr == 0b11, # MSR
+                Display("    msr: %016x", dbg_dout),
+             ),
              If(dbg_addr == 0b1000, # CR
                 Display("    cr : %016x", dbg_dout),
              ),