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versa_ecp5.py: Fix csr_address_width
authorLas Safin <me@las.rs>
Sat, 25 Sep 2021 15:49:30 +0000 (15:49 +0000)
committerLas Safin <me@las.rs>
Sat, 25 Sep 2021 15:57:24 +0000 (15:57 +0000)
versa_ecp5.py patch | blob | history

diff --git a/versa_ecp5.py b/versa_ecp5.py
index 18aca0eedf6f9f8ab3ecffa5fd6e98d305e92376..a8f2455ed6d43f8809d1c44833aa5d1889443789 100755 (executable)
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -29,7 +29,7 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
-        kwargs['csr_address_width'] = 12 # limit to 0x8000
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
         kwargs["l2_size"] = 0
         #bus_data_width = 16,