update Makefile to build 4ksrams

diff --git a/Makefile b/Makefile
index a56d541363fd1f9cb1f678dbaa961b2e93b28205..bd7734ec5b93f87c497be5954c1de51a7ef19f48 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,8 @@
 ls1804k:
        ./ls180soc.py --build --platform=ls180sram4k --num-srams=2
-       cp build/ls180/gateware/ls180.v .
-       cp build/ls180/gateware/mem.init .
-       cp build/ls180/gateware/mem_1.init .
-       cp build/ls180/gateware/mem_2.init .
-       cp build/ls180/gateware/mem_3.init .
-       cp build/ls180/gateware/mem_4.init .
+       cp build/ls180sram4k/gateware/ls180sram4k.v ./ls180.v
+       cp build/ls180sram4k/gateware/mem.init .
+       cp build/ls180sram4k/gateware/mem_1.init .
        cp libresoc/libresoc.v .
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'