disable PLL for litex build, new variant

diff --git a/libresoc/core.py b/libresoc/core.py
index 3340a0c4d13cd65960b80b85eccbea04eb61fda7..d7ed1e701a2b841fac65d7c4b24ce9cbc9fbd9f6 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -15,6 +15,7 @@ from litex.build.generic_platform import ConstraintManager
 
 CPU_VARIANTS = ["standard", "standard32", "standardjtag",
                 "standardjtagtestgpio", "ls180", "ls180sram4k",
+                "ls180nopll",
                 "standardjtagnoirq"]
 
 
@@ -269,7 +270,7 @@ class LibreSoC(CPU):
             ))
 
         # add clock select, pll output
-        if "ls180" in variant:
+        if "ls180" in variant and "pll" not in variant:
             self.pll_18_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_lck_o = Signal()

diff --git a/ls180soc.py b/ls180soc.py
index 44a4ce8c1c20ac0e650325a3db0201dbca7374dd..98210382813d3d5c86bab1eaf4f7b894ff50dd0b 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -315,7 +315,7 @@ class LibreSoCSim(SoCCore):
         #cpu_data_width = 32
         cpu_data_width = 64
 
-        variant = "ls180"
+        variant = "ls180nopll"
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['icp']  = 0xc0010000
@@ -418,14 +418,15 @@ class LibreSoCSim(SoCCore):
         self.submodules.crg = CRG(platform.request("sys_clk"),
                                   platform.request("sys_rst"))
 
-        # PLL/Clock Select
-        clksel_i = platform.request("sys_clksel_i")
-        pll18_o = platform.request("sys_pll_18_o")
-        pll_lck_o = platform.request("sys_pll_lck_o")
+        if hasattr(self.cpu, "clk_sel"):
+            # PLL/Clock Select
+            clksel_i = platform.request("sys_clksel_i")
+            pll18_o = platform.request("sys_pll_18_o")
+            pll_lck_o = platform.request("sys_pll_lck_o")
 
-        self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-        self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
-        self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
+            self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
+            self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL
+            self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
 
         #ram_init = []