add PLL clock loop-back into CPU

diff --git a/libresoc/core.py b/libresoc/core.py
index 6c39cd91716b13507116205b1f3c50f8924fca1a..178ebe8bfb0f38af2b9342b85a9bb8c3b303014c 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -276,9 +276,11 @@ class LibreSoC(CPU):
             self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_test_o = Signal()
+            self.pllclk_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
             self.cpu_params['o_pll_test_o'] = self.pll_test_o
+            self.cpu_params['o_pllclk_o'] = self.pllclk_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))

diff --git a/ls180soc.py b/ls180soc.py
index 6321b01dc19f27cbd0139811f6d94150f9562e25..a24083977bc4123de781c606d90f9740d340ccc9 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -433,6 +433,7 @@ class LibreSoCSim(SoCCore):
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
             self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
             self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
+            self.comb += self.cpu.clk.eq(self.cpu.pllclk_o) # PLL out into cpu
 
         #ram_init = []