add (commented-out) SVSRR0 DMI dump

diff --git a/sim.py b/sim.py
index 3a74235b24bf526ac8f444016e38b35d8b6dedc3..47c7684d01ec5e66467ff35b8d5fa0d3c63bdfb7 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -11,6 +11,7 @@ import os
 import argparse
 
 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState)
+from migen import Display as D
 
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
@@ -64,8 +65,8 @@ class LibreSoCSim(SoCSDRAM):
                     "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
-        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-        #            "tests/mmu/mmu.bin"
+        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+                    "tests/mmu/mmu.bin"
         #ram_fname = None
 
         # reserve XICS ICP and XICS memory addresses.
@@ -332,6 +333,7 @@ class LibreSoCSim(SoCSDRAM):
                 If(regnum == 43, Display(" HSPRG1: %016x", dbg_dout),), # HSPRG1
                 If(regnum == 44, Display("    XER: %016x", dbg_dout),), # XER
                 If(regnum == 45, Display("    TAR: %016x", dbg_dout),), # TAR
+                #If(regnum == 46, Display(" SVSRR0: %016x", dbg_dout),), # SVSRR0
              ),
             # also check if this is a "stat"
             If(dbg_addr == 1, # requested a STAT