whoops clk_sel_i renamed accidentally

diff --git a/libresoc/core.py b/libresoc/core.py
index c305d021f26bfaaad1487856f6156bb2653fd28e..2035df2a32e986b78d351df58734d8ecf593ec34 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -273,7 +273,7 @@ class LibreSoC(CPU):
             self.pll_18_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_ana_o = Signal()
-            self.cpu_params['i_clk__i'] = self.clk_sel
+            self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
             self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o