CHANGES

   1 [> 2020.XX, planned for July 2020
   2 ---------------------------------
   3
   4         [> Issues resolved
   5         ------------------
   6         - Fix flush_cpu_icache on VexRiscv.
   7         - Fix `.data` section placed in rom (#566)
   8
   9         [> Added Features
  10         ------------------
  11         - Properly integrate Minerva CPU.
  12         - Add nMigen dependency.
  13         - Pluggable CPUs.
  14         - BIOS history, autocomplete.
  15         - Improve boards's programmers.
  16         - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
  17         - Speedup Memtest using an LFSR.
  18         - Add LedChaser on boards.
  19         - Improve WishboneBridge.
  20         - Improve Diamond constraints.
  21         - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
  22         - Add CV32E40P CPU support (ex RI5CY).
  23         - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
  24         - Add Symbiflow experimental support on Arty.
  25         - Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
  26         - Simplify boot with boot.json configuration file.
  27         - Revert to a single crt0 (avoid ctr/xip variants).
  28         - Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
  29         - Add AXI-Lite bus standard support.
  30         - Add VexRiscv SMP CPU support.
  31
  32         [> API changes/Deprecation
  33         --------------------------
  34         - Add --build --load arguments to targets.
  35         - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
  36         - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
  37         - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
  38         - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
  39         - Rename --gateware-toolchain target parameter to --toolchain.
  40         - Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
  41
  42 [> 2020.04, released April 28th, 2020
  43 -------------------------------------
  44
  45         [> Description
  46         --------------
  47         First release of LiteX and the ecosystem of cores!
  48
  49         LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
  50         Cores/SoCs (with or without CPU).
  51
  52         The common components of a SoC are provided directly:
  53         - Buses and Streams (Wishbone, AXI, Avalon-ST)
  54         - Interconnect
  55         - Common cores (RAM, ROM, Timer, UART, etc...)
  56         - CPU wrappers/integration
  57         - etc...
  58         And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
  59         PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
  60
  61         It also provides build backends for open-source and vendors toolchains.
  62
  63         [> Issues resolved
  64         ------------------
  65         - NA
  66
  67         [> Added Features
  68         ------------------
  69         - NA
  70
  71         [> API changes/Deprecation
  72         --------------------------
  73         - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.