Makefile

   1 CFLAGS=-O3 -Wall
   2 CXXFLAGS=-g -g
   3
   4 YOSYS     ?= yosys
   5 NEXTPNR   ?= nextpnr-ecp5
   6 ECPPACK   ?= ecppack
   7 OPENOCD   ?= openocd
   8
   9 all = ls2_verilator
  10
  11 all: $(all)
  12
  13 uart_files = $(wildcard ../uart16550/rtl/verilog/*.v)
  14
  15 # Verilator sim
  16 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
  17 ifeq (, $(VERILATOR_ROOT))
  18 $(soc_dram_tbs):
  19         $(error "Verilator is required to make this target !")
  20 else
  21
  22 VERILATOR_CFLAGS=-O3
  23 VERILATOR_FLAGS=-O3
  24
  25 endif
  26
  27 # Hello world
  28 MEMORY_SIZE=8192
  29 #RAM_INIT_FILE=hello_world/hello_world.bin
  30 #RAM_INIT_FILE=../microwatt2/tests/xics/xics.bin
  31 RAM_INIT_FILE=coldboot/coldboot.bin
  32 SIM_MAIN_BRAM=false
  33
  34 # Micropython
  35 #MEMORY_SIZE=393216
  36 #RAM_INIT_FILE=micropython/firmware.bin
  37
  38 # Linux
  39 #MEMORY_SIZE=536870912
  40 #RAM_INIT_FILE=dtbImage.microwatt.bin
  41 #SIM_MAIN_BRAM=false
  42 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
  43
  44 FPGA_TARGET ?= verilator
  45
  46 ifeq ($(FPGA_TARGET), verilator)
  47 RESET_LOW=true
  48 CLK_INPUT=100000000
  49 CLK_FREQUENCY=100000000
  50 clkgen=fpga/clk_gen_bypass.vhd
  51 endif
  52
  53 ls2.v: src/ls2.py
  54         python3 src/ls2.py sim $(RAM_INIT_FILE)
  55
  56 # Need to investigate why yosys is hitting verilator warnings,
  57 # and eventually turn on -Wall
  58 microwatt-verilator: ls2.v \
  59                      verilator/microwatt-verilator.cpp \
  60                      verilator/uart-verilator.c
  61         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
  62         -DDATA_BUS_WIDTH_8 \
  63     --assert \
  64         --top-module top \
  65     --cc ls2.v \
  66     --cc external_core_top.v \
  67     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \
  68     -o $@ -I../uart16550/rtl/verilog \
  69         -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \
  70             -Wno-BLKANDNBLK \
  71             -Wno-COMBDLY  \
  72             -Wno-CASEINCOMPLETE \
  73             -Wno-WIDTH \
  74             -Wno-TIMESCALEMOD \
  75          --savable \
  76          --trace \
  77         #    --unroll-count 256 \
  78         #    --output-split 5000 \
  79         #    --output-split-cfuncs 500 \
  80         #    --output-split-ctrace 500 \
  81         make -C obj_dir -f Vtop.mk
  82         @cp -f obj_dir/microwatt-verilator microwatt-verilator
  83
  84 clean:
  85         rm -fr obj_dir microwatt-verilator ls2.v
  86
  87 .PHONY: all clean