code-comments for when ASyncBridge is deployed

diff --git a/src/ls2.py b/src/ls2.py
index 045ea4bcb43bd2d8c9cc6b7e5b078381905d9645..4819cdc23ca7ee285ee36e493395ff85dfc67564 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -379,8 +379,11 @@ class DDR3SoC(SoC, Elaboratable):
             # HOWEVER, when the ASyncBridge is deployed, the two domains
             # must NOT be renamed, instead this used:
             #drs = lambda x: x
-            # and then the ASyncBridge takes care of it.
-            # but, back in ecp5_crg.py,
+            # and then the ASyncBridge takes care of the two.
+            # but, back in ecp5_crg.py, when ASyncBridge is added,
+            # dram_clk_freq must be passed to ECP5CRG, which will call
+            # ECP5CRG.phase2_domain on your behalf, setting up the
+            # necessary dramsync2x which is needed for the xdr=4 IOpads
 
             if fpga == 'sim':
                 self.ddrphy = FakePHY(module=ddrmodule,