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Put sysclk2x back under system reset control
authorRaptor Engineering Development Team <support@raptorengineering.com>
Sun, 10 Apr 2022 02:15:35 +0000 (21:15 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Sun, 10 Apr 2022 02:15:35 +0000 (21:15 -0500)
src/ecp5_crg.py patch | blob | history

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 86358d48e91d26dcfc6eb4d9e821b99063cce242..d588376c4ee7388f797042ef94924ca3d74ba474 100644 (file)
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
-        cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True)
+        cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)