add spi for orangecrab

diff --git a/src/ls2.py b/src/ls2.py
index 4ea9699e910ce3795b030a8c051385fd0c4446bc..41ab7179f0f600d58f13efc619cd5fbebba2ca1b 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -547,6 +547,7 @@ class DDR3SoC(SoC, Elaboratable):
         if spi_0_pins is not None and fpga in ['sim',
                                              'isim',
                                              'rcs_arctic_tern_bmc_card',
+                                             'orangecrab',
                                              'versa_ecp5',
                                              'versa_ecp5_85',
                                              'arty_a7']:
@@ -557,6 +558,7 @@ class DDR3SoC(SoC, Elaboratable):
             if fpga in ['versa_ecp5',
                         'versa_ecp5_85',
                         'rcs_arctic_tern_bmc_card',
+                        'orangecrab',
                         'isim']:
                 spi0_is_lattice_ecp5_clk = True
 
@@ -953,6 +955,33 @@ def build_platform(fpga, firmware):
         platform.add_resources(spi_0_ios)
         spi_0_pins = platform.request("spi_0", 0)
 
+
+    if platform is not None and \
+       fpga in ['orangecrab']:
+       # spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+       # spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+       # spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+       # spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+       # cs_n="U17", clk="U16", miso="T18", mosi="U18", wp_n="R18", hold_n="N18"
+        # each pin needs a separate direction control
+        spi_0_ios = [
+            Resource("spi_0", 0,
+                     Subsignal("dq0",  Pins("U18", dir="io")), #mosi
+                     Subsignal("dq1",  Pins("T18", dir="io")), #miso
+                     Subsignal("dq2",  Pins("R18", dir="io")), #wp_n
+                     Subsignal("dq3",  Pins("N18", dir="io")), #hold_n
+                     # We use USRMCLK instead for clk
+                     # todo: read docs
+                     Subsignal("cs_n", Pins("U17", dir="o")),
+                     # Subsignal("clk",  Pins("U16", dir="o")),
+                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+        ]
+        platform.add_resources(spi_0_ios)
+        spi_0_pins = platform.request("spi_0", 0, dir={"cs_n":"o"},
+                                                  xdr={"dq0":1, "dq1": 1,
+                                                       "dq2":1, "dq3": 1,
+                                                       "cs_n":0})
+
     print ("spiflash pins", spi_0_pins)
 
     # Get Ethernet RMII resource pins