move hyperram to 0x0000_00000 and 0x2000_0000

to start memory range 0-64mbytes
also document the startup process for arty a7-100t which is a bit arcane

diff --git a/README.txt b/README.txt
index bedf8c5b25a4e7aa538775617fc14884142f2f44..1b51d134785e86771b6541fa015d0c8f147469f2 100644 (file)
--- a/README.txt
+++ b/README.txt
@@ -6,3 +6,14 @@ openocd -f top-openocd.cfg \
 
 ecpprog -o 0 binary.bin
 
+# Arty A7-100t
+
+* apt install gcc-powerpc64le-linux-gnu
+* git clone -b microwatt-5.7 https://git.kernel.org/pub/scm/linux/kernel/git/joel/microwatt.git
+* cd microwatt
+* CROSS_COMPILE="ccache powerpc64le-linux-gnu-" ARCH=powerpc make -j8 O=microwatt
+* git clone https://github.com/antonblanchard/microwatt
+* git clone https://github.com/quartiq/bscan_spi_bitstreams
+  and update openocd/bscan_spi_xc7a100t.bin in microwatt
+* python3 openocd/flash-arty -f a100 -a 0x600000 -t bin dtbImage.microwatt
+* xc3sprog -c nexys4 libresoc.bit (more likely, build/top.bit)

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 260974bf0584e2f36c99f41d7c6099a4ea0282d3..5987e7475accf5e1019a64d17cc6dee5c68b8255 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -269,7 +269,7 @@ int main(void) {
             uart_writeuint32(k);
             puts(" ");
             uart_writeuint32(tmp);
-            puts("\n");
+            puts("\r\n");
         }
     }
 #endif
@@ -278,7 +278,7 @@ int main(void) {
         //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
          // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
          // tmp = readl((unsigned long)&(qspi[0]));
-        for (int i=0;i<256;i++) {
+        for (int i=0;i<2;i++) {
           tmp = readl((unsigned long)&(qspi[i]));
           uart_writeuint32(tmp);
           puts(" ");
@@ -321,9 +321,10 @@ int main(void) {
     }
 #endif
 #if 0
-       volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
+       volatile uint32_t *hyperram = (uint32_t*)0x00000000; // at 0x0 for arty
     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
     tmp = readl((unsigned long)&(hyperram[0]));
+    int i = 0;
     while (1) {
         unsigned char c = getchar();
         putchar(c);

diff --git a/src/ls2.py b/src/ls2.py
index 5a35a8dc80bccc0027647a81e4a1fa2fbb6af698..283eb410e7c16bb924001255f8618f15cba6f205 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -534,7 +534,8 @@ class DDR3SoC(SoC, Elaboratable):
 
         # additional SRAM at address if DRAM is not also at 0x0
         # (TODO, check Flash, and HyperRAM as well)
-        if (ddr_pins is None or ddr_addr != 0x0) and fw_addr != 0:
+        if ((ddr_pins is None or ddr_addr != 0x0) and fw_addr != 0 and
+            hyperram_addr[0] != 0x0):
             print ("SRAM 0x8000 at address 0x0")
             sram_width = 32
             self.sram = SRAMPeripheral(size=0x8000,
@@ -996,6 +997,7 @@ def build_platform(fpga, firmware):
 
     # Get HyperRAM pins
     hyperram_pins = []
+    hyperram_addr = [0xa000_0000]
     if platform is None:
         hyperram_pins = [HyperRAMPads()]
     elif fpga in ['isim']:
@@ -1023,6 +1025,8 @@ def build_platform(fpga, firmware):
         hyperram_pins = [platform.request("hyperram", 0),
                          platform.request("hyperram", 1)]
         print ("arty a7 hyperram", hyperram_ios)
+        hyperram_addr=[0x0000_0000,  # HYPERRAM_BASE1
+                       0x0200_0000] # HYPERRAM_BASE2
     # VERSA ECP5
     elif False and platform is not None and fpga in \
                 ['versa_ecp5', 'versa_ecp5_85']:
@@ -1045,8 +1049,7 @@ def build_platform(fpga, firmware):
                   spi0_cfg_addr=0xc0006000, # SPI0_CTRL_BASE
                   eth0_cfg_addr=0xc000c000, # ETH0_CTRL_BASE (4k)
                   eth0_irqno=1,             # ETH0_IRQ number (match microwatt)
-                  hyperram_addr=[0xa0000000,  # HYPERRAM_BASE1
-                                 0xa2000000], # HYPERRAM_BASE2
+                  hyperram_addr=hyperram_addr, # determined above
                   fw_addr=fw_addr,
                   #fw_addr=None,
                   ddr_pins=ddr_pins,