Reorganize resource taxonomy.

The current hierarchy isn't particularly well suited to resources
like SDRAM or NOR flash, so make it much less fine-grained but easier
to use and less nitpicky.

diff --git a/nmigen_boards/arty_a7.py b/nmigen_boards/arty_a7.py
index 57fe765cfc5be5f19a534801068aa4fa869b0d0a..ba4a9db0f2602d3a55dcbc5ec362f8e60f0c3cb0 100644 (file)
--- a/nmigen_boards/arty_a7.py
+++ b/nmigen_boards/arty_a7.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_7series import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["ArtyA7Platform"]

diff --git a/nmigen_boards/atlys.py b/nmigen_boards/atlys.py
index d70c6d03b4712c7b91fbf6313af8e9885c1568bb..080fecdc932053e257b0f9b63a2f45c730cd27e0 100644 (file)
--- a/nmigen_boards/atlys.py
+++ b/nmigen_boards/atlys.py
@@ -3,7 +3,7 @@ import textwrap
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_spartan_3_6 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["AtlysPlatform"]

diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index 385401d369d4e63b3f970e384e5e30af20625e44..75c9ac99e9fb980d09131f763144d04c9dc045b7 100644 (file)
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["BlackIcePlatform"]

diff --git a/nmigen_boards/blackice_ii.py b/nmigen_boards/blackice_ii.py
index 86e381d70a198f8b7abdc39a4377eb75d0d734e1..a679bda966500d8dc9655d963281b0ff10713aca 100644 (file)
--- a/nmigen_boards/blackice_ii.py
+++ b/nmigen_boards/blackice_ii.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["BlackIceIIPlatform"]

diff --git a/nmigen_boards/dev/__init__.py b/nmigen_boards/dev/__init__.py
deleted file mode 100644 (file)
index db4703f..0000000
--- a/nmigen_boards/dev/__init__.py
+++ /dev/null
@@ -1,5 +0,0 @@
-from .user import LEDResources, RGBLEDResource, ButtonResources, SwitchResources
-from .uart import UARTResource
-from .spi import SPIResource
-from .flash import SPIFlashResources
-from .sram import SRAMResource

diff --git a/nmigen_boards/dev/display.py b/nmigen_boards/dev/display.py
deleted file mode 100644 (file)
index 0431b58..0000000
--- a/nmigen_boards/dev/display.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["Display7SegResource"]
-
-
-def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False, attrs=None):
-    ios = []
-    ios.append(Subsignal("a", Pins(a, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("c", Pins(c, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("d", Pins(d, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("e", Pins(e, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("f", Pins(f, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
-    if dp is not None:
-        ios.append(Subsignal("dp", Pins(dp, dir="o", assert_width=1)))
-    if attrs is not None:
-        ios.append(attrs)
-    return Resource.family(*args, default_name="display_7seg", ios=ios)

diff --git a/nmigen_boards/dev/flash.py b/nmigen_boards/dev/flash.py
deleted file mode 100644 (file)
index 817b6d4..0000000
--- a/nmigen_boards/dev/flash.py
+++ /dev/null
@@ -1,38 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["SPIFlashResources"]
-
-
-def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
-    resources = []
-
-    io_all = []
-    if attrs is not None:
-        io_all.append(attrs)
-    io_all.append(Subsignal("cs",  PinsN(cs, dir="o")))
-    io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
-
-    io_1x = list(io_all)
-    io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
-    io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
-    if wp is not None and hold is not None:
-        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", assert_width=1)))
-        io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
-    resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
-                                     name_suffix="1x"))
-
-    io_2x = list(io_all)
-    io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
-                                      assert_width=2)))
-    resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
-                                     name_suffix="2x"))
-
-    if wp is not None and hold is not None:
-        io_4x = list(io_all)
-        io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
-                                          assert_width=4)))
-        resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
-                                         name_suffix="4x"))
-
-    return resources

diff --git a/nmigen_boards/dev/sd.py b/nmigen_boards/dev/sd.py
deleted file mode 100644 (file)
index 8fdbcbe..0000000
--- a/nmigen_boards/dev/sd.py
+++ /dev/null
@@ -1,46 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["SDCardResources"]
-
-
-def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None,
-                    cd=None, wp=None, attrs=None):
-    resources = []
-
-    io_common = []
-    if attrs is not None:
-        io_common.append(attrs)
-    if cd is not None:
-        io_common.append(Subsignal("cd", Pins(cd, dir="i", assert_width=1)))
-    if wp is not None:
-        io_common.append(Subsignal("wp", PinsN(wp, dir="i", assert_width=1)))
-
-    io_native = list(io_common)
-    io_native.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
-    io_native.append(Subsignal("cmd", Pins(cmd, dir="o", assert_width=1)))
-
-    io_1bit = list(io_native)
-    io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", assert_width=1)))
-    if dat3 is not None: # works as electronic card detect
-        io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", assert_width=1)))
-    resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
-                                     name_suffix="1bit"))
-
-    if dat1 is not None and dat2 is not None and dat3 is not None:
-        io_4bit = list(io_native)
-        io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
-                                             assert_width=4)))
-        resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
-                                         name_suffix="4bit"))
-
-    if dat3 is not None:
-        io_spi = list(io_common)
-        io_spi.append(Subsignal("cs", PinsN(dat3, dir="io"))) # doubles as electronic card detect
-        io_spi.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
-        io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", assert_width=1)))
-        io_spi.append(Subsignal("miso", Pins(dat0, dir="i", assert_width=1)))
-        resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
-                                         name_suffix="spi"))
-
-    return resources

diff --git a/nmigen_boards/dev/spi.py b/nmigen_boards/dev/spi.py
deleted file mode 100644 (file)
index 2d045bc..0000000
--- a/nmigen_boards/dev/spi.py
+++ /dev/null
@@ -1,33 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["SPIResource"]
-
-
-def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, attrs=None, role="host"):
-    assert role in ("host", "device")
-
-    io = []
-    if role == "host":
-        io.append(Subsignal("cs", PinsN(cs, dir="o")))
-        io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
-        io.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
-        io.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
-    else:  # device
-        io.append(Subsignal("cs", PinsN(cs, dir="i", assert_width=1)))
-        io.append(Subsignal("clk", Pins(clk, dir="i", assert_width=1)))
-        io.append(Subsignal("mosi", Pins(mosi, dir="i", assert_width=1)))
-        io.append(Subsignal("miso", Pins(miso, dir="oe", assert_width=1)))
-    if int is not None:
-        if role == "host":
-            io.append(Subsignal("int", Pins(int, dir="i")))
-        else:
-            io.append(Subsignal("int", Pins(int, dir="oe", assert_width=1)))
-    if reset is not None:
-        if role == "host":
-            io.append(Subsignal("reset", Pins(reset, dir="o")))
-        else:
-            io.append(Subsignal("reset", Pins(reset, dir="i", assert_width=1)))
-    if attrs is not None:
-        io.append(attrs)
-    return Resource.family(*args, default_name="spi", ios=io)

diff --git a/nmigen_boards/dev/sram.py b/nmigen_boards/dev/sram.py
deleted file mode 100644 (file)
index 14e31ce..0000000
--- a/nmigen_boards/dev/sram.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["SRAMResource"]
-
-
-def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
-    io = []
-    io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
-    if oe is not None:
-        # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
-        io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
-    io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
-    io.append(Subsignal("a", Pins(a, dir="o")))
-    io.append(Subsignal("d", Pins(d, dir="io")))
-    if dm is not None:
-        io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
-    if attrs is not None:
-        io.append(attrs)
-    return Resource.family(*args, default_name="sram", ios=io)

diff --git a/nmigen_boards/dev/uart.py b/nmigen_boards/dev/uart.py
deleted file mode 100644 (file)
index 706e50c..0000000
--- a/nmigen_boards/dev/uart.py
+++ /dev/null
@@ -1,42 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["UARTResource", "IrDAResource"]
-
-
-def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
-                 attrs=None):
-    io = []
-    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
-    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
-    if rts is not None:
-        io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
-    if cts is not None:
-        io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
-    if dtr is not None:
-        io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
-    if dsr is not None:
-        io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
-    if dcd is not None:
-        io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
-    if ri is not None:
-        io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
-    if attrs is not None:
-        io.append(attrs)
-    return Resource.family(*args, default_name="uart", ios=io)
-
-
-def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
-    # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
-    # be specified, and it is mapped to a logic level en subsignal.
-    assert (en is not None) ^ (sd is not None)
-    io = []
-    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
-    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
-    if en is not None:
-        io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
-    if sd is not None:
-        io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
-    if attrs is not None:
-        io.append(attrs)
-    return Resource("irda", number, *io)

diff --git a/nmigen_boards/dev/user.py b/nmigen_boards/dev/user.py
deleted file mode 100644 (file)
index 8faa736..0000000
--- a/nmigen_boards/dev/user.py
+++ /dev/null
@@ -1,43 +0,0 @@
-from nmigen.build import *
-
-
-__all__ = ["LEDResources", "RGBLEDResource", "ButtonResources", "SwitchResources"]
-
-
-def _SplitResources(*args, pins, invert=False, attrs=None, default_name, dir):
-    assert isinstance(pins, (str, list, dict))
-
-    if isinstance(pins, str):
-        pins = pins.split()
-    if isinstance(pins, list):
-        pins = dict(enumerate(pins))
-
-    resources = []
-    for number, pin in pins.items():
-        ios = [Pins(pin, dir=dir, invert=invert)]
-        if attrs is not None:
-            ios.append(attrs)
-        resources.append(Resource.family(*args, number, default_name=default_name, ios=ios))
-    return resources
-
-
-def LEDResources(*args, **kwargs):
-    return _SplitResources(*args, **kwargs, default_name="led", dir="o")
-
-
-def RGBLEDResource(*args, r, g, b, invert=False, attrs=None):
-    ios = []
-    ios.append(Subsignal("r", Pins(r, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
-    ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
-    if attrs is not None:
-        ios.append(attrs)
-    return Resource.family(*args, default_name="rgb_led", ios=ios)
-
-
-def ButtonResources(*args, **kwargs):
-    return _SplitResources(*args, **kwargs, default_name="button", dir="i")
-
-
-def SwitchResources(*args, **kwargs):
-    return _SplitResources(*args, **kwargs, default_name="switch", dir="i")

diff --git a/nmigen_boards/ext/__init__.py b/nmigen_boards/ext/__init__.py
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/nmigen_boards/ext/pmod.py b/nmigen_boards/ext/pmod.py
deleted file mode 100644 (file)
index 331352c..0000000
--- a/nmigen_boards/ext/pmod.py
+++ /dev/null
@@ -1,94 +0,0 @@
-# Reference: https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf
-
-from nmigen.build import *
-
-
-__all__ = [
-    "PmodGPIOType1Resource",
-    "PmodSPIType2Resource",
-    "PmodSPIType2AResource",
-    "PmodUARTType3Resource",
-    "PmodUARTType4Resource",
-    "PmodUARTType4AResource",
-    "PmodHBridgeType5Resource",
-    "PmodDualHBridgeType6Resource",
-]
-
-
-def PmodGPIOType1Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Pins("1 2 3 4", dir="io", conn=("pmod", pmod)),
-        extras=extras
-    )
-
-
-def PmodSPIType2Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("cs_n",  Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("clk",   Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("mosi",  Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("miso",  Pins("4", dir="i", conn=("pmod", pmod))),
-        extras=extras
-    )
-
-
-def PmodSPIType2AResource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("cs_n",  Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("clk",   Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("mosi",  Pins("3", dir="o", conn=("pmod", pmod))),
-        Subsignal("miso",  Pins("4", dir="i", conn=("pmod", pmod))),
-        Subsignal("int",   Pins("7", dir="i", conn=("pmod", pmod))),
-        Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
-        extras=extras
-        )
-
-
-def PmodUARTType3Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("cts",   Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("rts",   Pins("2", dir="i", conn=("pmod", pmod))),
-        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("tx",    Pins("4", dir="o", conn=("pmod", pmod))),
-        extras=extras
-    )
-
-
-def PmodUARTType4Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("cts",   Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("tx",    Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("rts",   Pins("4", dir="o", conn=("pmod", pmod))),
-        extras=extras
-    )
-
-
-def PmodUARTType4AResource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("cts",   Pins("1", dir="i", conn=("pmod", pmod))),
-        Subsignal("tx",    Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("rts",   Pins("4", dir="o", conn=("pmod", pmod))),
-        Subsignal("int",   Pins("7", dir="i", conn=("pmod", pmod))),
-        Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
-        extras=extras
-    )
-
-
-def PmodHBridgeType5Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("dir",   Pins("1", dir="o", conn=("pmod", pmod))),
-        Subsignal("en",    Pins("2", dir="o", conn=("pmod", pmod))),
-        Subsignal("sa",    Pins("3", dir="i", conn=("pmod", pmod))),
-        Subsignal("sb",    Pins("4", dir="i", conn=("pmod", pmod))),
-        extras=extras
-    )
-
-
-def PmodDualHBridgeType6Resource(name, number, *, pmod, extras=None):
-    return Resource(name, number,
-        Subsignal("dir",   Pins("1 3", dir="o", conn=("pmod", pmod))),
-        Subsignal("en",    Pins("2 4", dir="o", conn=("pmod", pmod))),
-        extras=extras
-    )

diff --git a/nmigen_boards/extensions/__init__.py b/nmigen_boards/extensions/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/nmigen_boards/extensions/pmod.py b/nmigen_boards/extensions/pmod.py
new file mode 100644 (file)
index 0000000..331352c
--- /dev/null
+++ b/nmigen_boards/extensions/pmod.py
@@ -0,0 +1,94 @@
+# Reference: https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf
+
+from nmigen.build import *
+
+
+__all__ = [
+    "PmodGPIOType1Resource",
+    "PmodSPIType2Resource",
+    "PmodSPIType2AResource",
+    "PmodUARTType3Resource",
+    "PmodUARTType4Resource",
+    "PmodUARTType4AResource",
+    "PmodHBridgeType5Resource",
+    "PmodDualHBridgeType6Resource",
+]
+
+
+def PmodGPIOType1Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Pins("1 2 3 4", dir="io", conn=("pmod", pmod)),
+        extras=extras
+    )
+
+
+def PmodSPIType2Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("cs_n",  Pins("1", dir="o", conn=("pmod", pmod))),
+        Subsignal("clk",   Pins("2", dir="o", conn=("pmod", pmod))),
+        Subsignal("mosi",  Pins("3", dir="o", conn=("pmod", pmod))),
+        Subsignal("miso",  Pins("4", dir="i", conn=("pmod", pmod))),
+        extras=extras
+    )
+
+
+def PmodSPIType2AResource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("cs_n",  Pins("1", dir="o", conn=("pmod", pmod))),
+        Subsignal("clk",   Pins("2", dir="o", conn=("pmod", pmod))),
+        Subsignal("mosi",  Pins("3", dir="o", conn=("pmod", pmod))),
+        Subsignal("miso",  Pins("4", dir="i", conn=("pmod", pmod))),
+        Subsignal("int",   Pins("7", dir="i", conn=("pmod", pmod))),
+        Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
+        extras=extras
+        )
+
+
+def PmodUARTType3Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("cts",   Pins("1", dir="o", conn=("pmod", pmod))),
+        Subsignal("rts",   Pins("2", dir="i", conn=("pmod", pmod))),
+        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
+        Subsignal("tx",    Pins("4", dir="o", conn=("pmod", pmod))),
+        extras=extras
+    )
+
+
+def PmodUARTType4Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("cts",   Pins("1", dir="i", conn=("pmod", pmod))),
+        Subsignal("tx",    Pins("2", dir="o", conn=("pmod", pmod))),
+        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
+        Subsignal("rts",   Pins("4", dir="o", conn=("pmod", pmod))),
+        extras=extras
+    )
+
+
+def PmodUARTType4AResource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("cts",   Pins("1", dir="i", conn=("pmod", pmod))),
+        Subsignal("tx",    Pins("2", dir="o", conn=("pmod", pmod))),
+        Subsignal("rx",    Pins("3", dir="i", conn=("pmod", pmod))),
+        Subsignal("rts",   Pins("4", dir="o", conn=("pmod", pmod))),
+        Subsignal("int",   Pins("7", dir="i", conn=("pmod", pmod))),
+        Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))),
+        extras=extras
+    )
+
+
+def PmodHBridgeType5Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("dir",   Pins("1", dir="o", conn=("pmod", pmod))),
+        Subsignal("en",    Pins("2", dir="o", conn=("pmod", pmod))),
+        Subsignal("sa",    Pins("3", dir="i", conn=("pmod", pmod))),
+        Subsignal("sb",    Pins("4", dir="i", conn=("pmod", pmod))),
+        extras=extras
+    )
+
+
+def PmodDualHBridgeType6Resource(name, number, *, pmod, extras=None):
+    return Resource(name, number,
+        Subsignal("dir",   Pins("1 3", dir="o", conn=("pmod", pmod))),
+        Subsignal("en",    Pins("2 4", dir="o", conn=("pmod", pmod))),
+        extras=extras
+    )

diff --git a/nmigen_boards/fomu_hacker.py b/nmigen_boards/fomu_hacker.py
index 0ddfe490b5ac66690fa9feacfc553fc64a594b57..37dda3421f428c11656099d0bc9d88da39a28948 100644 (file)
--- a/nmigen_boards/fomu_hacker.py
+++ b/nmigen_boards/fomu_hacker.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["FomuHackerPlatform"]

diff --git a/nmigen_boards/ice40_hx1k_blink_evn.py b/nmigen_boards/ice40_hx1k_blink_evn.py
index ae46f248390b2a88734cfd23054d8b1c5237a0a2..03d91a0d31e2e6155b7439e1f13130b3626e1675 100644 (file)
--- a/nmigen_boards/ice40_hx1k_blink_evn.py
+++ b/nmigen_boards/ice40_hx1k_blink_evn.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["ICE40HX1KBlinkEVNPlatform"]

diff --git a/nmigen_boards/ice40_hx8k_b_evn.py b/nmigen_boards/ice40_hx8k_b_evn.py
index ce55e81df805d3261bde27ed4339f57fa176a14b..46b0180f222d4247862a45510b6cb76c6d98ba34 100644 (file)
--- a/nmigen_boards/ice40_hx8k_b_evn.py
+++ b/nmigen_boards/ice40_hx8k_b_evn.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["ICE40HX8KBEVNPlatform"]

diff --git a/nmigen_boards/icebreaker.py b/nmigen_boards/icebreaker.py
index 2f3034cff3d0d9dc33d46c35e656c45258dcb4eb..cc2ddf9374fc39b70790cf0c7baf84436f98eceb 100644 (file)
--- a/nmigen_boards/icebreaker.py
+++ b/nmigen_boards/icebreaker.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["ICEBreakerPlatform"]

diff --git a/nmigen_boards/icestick.py b/nmigen_boards/icestick.py
index 763eaee4d57df2bb8f78c958ace104547063609c..c6cdfe7f2ac444c4764494495506e741a7eed147 100644 (file)
--- a/nmigen_boards/icestick.py
+++ b/nmigen_boards/icestick.py
@@ -3,8 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
-from .dev.uart import IrDAResource
+from .resources import *
 
 
 __all__ = ["ICEStickPlatform"]

diff --git a/nmigen_boards/kc705.py b/nmigen_boards/kc705.py
index bc889deaa92067cac7d37d6887f021833794b47f..149f8663497cac84db6edc548655ef70501bf103 100644 (file)
--- a/nmigen_boards/kc705.py
+++ b/nmigen_boards/kc705.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_7series import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["KC705Platform"]

diff --git a/nmigen_boards/mercury.py b/nmigen_boards/mercury.py
index ea562491baeff0c6d695fbfa778ef6329ce78126..85bfb1db81f9a0cbafceb0193dc7a19846d0f6c1 100644 (file)
--- a/nmigen_boards/mercury.py
+++ b/nmigen_boards/mercury.py
@@ -3,8 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_spartan_3_6 import *
-from .dev import *
-from .dev.display import Display7SegResource
+from .resources import *
 
 
 __all__ = ["MercuryPlatform"]

diff --git a/nmigen_boards/numato_mimas.py b/nmigen_boards/numato_mimas.py
index c0945286d085a70d6b28c1e5d06886436c7a9cf5..2e76c69edae93a76d89e03efc7c6ac09cc26d3a5 100644 (file)
--- a/nmigen_boards/numato_mimas.py
+++ b/nmigen_boards/numato_mimas.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_spartan_3_6 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["NumatoMimasPlatform"]

diff --git a/nmigen_boards/resources/__init__.py b/nmigen_boards/resources/__init__.py
new file mode 100644 (file)
index 0000000..531eb5e
--- /dev/null
+++ b/nmigen_boards/resources/__init__.py
@@ -0,0 +1,4 @@
+from .display import *
+from .interface import *
+from .memory import *
+from .user import *

diff --git a/nmigen_boards/resources/display.py b/nmigen_boards/resources/display.py
new file mode 100644 (file)
index 0000000..0431b58
--- /dev/null
+++ b/nmigen_boards/resources/display.py
@@ -0,0 +1,20 @@
+from nmigen.build import *
+
+
+__all__ = ["Display7SegResource"]
+
+
+def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False, attrs=None):
+    ios = []
+    ios.append(Subsignal("a", Pins(a, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("c", Pins(c, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("d", Pins(d, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("e", Pins(e, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("f", Pins(f, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
+    if dp is not None:
+        ios.append(Subsignal("dp", Pins(dp, dir="o", assert_width=1)))
+    if attrs is not None:
+        ios.append(attrs)
+    return Resource.family(*args, default_name="display_7seg", ios=ios)

diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
new file mode 100644 (file)
index 0000000..7ab0518
--- /dev/null
+++ b/nmigen_boards/resources/interface.py
@@ -0,0 +1,72 @@
+from nmigen.build import *
+
+
+__all__ = ["UARTResource", "IrDAResource", "SPIResource"]
+
+
+def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
+                 attrs=None):
+    io = []
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
+    if rts is not None:
+        io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
+    if cts is not None:
+        io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
+    if dtr is not None:
+        io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
+    if dsr is not None:
+        io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
+    if dcd is not None:
+        io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
+    if ri is not None:
+        io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="uart", ios=io)
+
+
+def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
+    # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
+    # be specified, and it is mapped to a logic level en subsignal.
+    assert (en is not None) ^ (sd is not None)
+
+    io = []
+    io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+    io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
+    if en is not None:
+        io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
+    if sd is not None:
+        io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource("irda", number, *io)
+
+
+def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, attrs=None, role="host"):
+    assert role in ("host", "device")
+
+    io = []
+    if role == "host":
+        io.append(Subsignal("cs", PinsN(cs, dir="o")))
+        io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
+        io.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
+        io.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
+    else:  # device
+        io.append(Subsignal("cs", PinsN(cs, dir="i", assert_width=1)))
+        io.append(Subsignal("clk", Pins(clk, dir="i", assert_width=1)))
+        io.append(Subsignal("mosi", Pins(mosi, dir="i", assert_width=1)))
+        io.append(Subsignal("miso", Pins(miso, dir="oe", assert_width=1)))
+    if int is not None:
+        if role == "host":
+            io.append(Subsignal("int", Pins(int, dir="i")))
+        else:
+            io.append(Subsignal("int", Pins(int, dir="oe", assert_width=1)))
+    if reset is not None:
+        if role == "host":
+            io.append(Subsignal("reset", Pins(reset, dir="o")))
+        else:
+            io.append(Subsignal("reset", Pins(reset, dir="i", assert_width=1)))
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="spi", ios=io)

diff --git a/nmigen_boards/resources/memory.py b/nmigen_boards/resources/memory.py
new file mode 100644 (file)
index 0000000..809035c
--- /dev/null
+++ b/nmigen_boards/resources/memory.py
@@ -0,0 +1,96 @@
+from nmigen.build import *
+
+
+__all__ = ["SPIFlashResources", "SDCardResources", "SRAMResource"]
+
+
+def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
+    resources = []
+
+    io_all = []
+    if attrs is not None:
+        io_all.append(attrs)
+    io_all.append(Subsignal("cs",  PinsN(cs, dir="o")))
+    io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
+
+    io_1x = list(io_all)
+    io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
+    io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
+    if wp is not None and hold is not None:
+        io_1x.append(Subsignal("wp",   PinsN(wp,   dir="o", assert_width=1)))
+        io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
+    resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
+                                     name_suffix="1x"))
+
+    io_2x = list(io_all)
+    io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
+                                      assert_width=2)))
+    resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
+                                     name_suffix="2x"))
+
+    if wp is not None and hold is not None:
+        io_4x = list(io_all)
+        io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
+                                          assert_width=4)))
+        resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
+                                         name_suffix="4x"))
+
+    return resources
+
+
+def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None,
+                    cd=None, wp=None, attrs=None):
+    resources = []
+
+    io_common = []
+    if attrs is not None:
+        io_common.append(attrs)
+    if cd is not None:
+        io_common.append(Subsignal("cd", Pins(cd, dir="i", assert_width=1)))
+    if wp is not None:
+        io_common.append(Subsignal("wp", PinsN(wp, dir="i", assert_width=1)))
+
+    io_native = list(io_common)
+    io_native.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
+    io_native.append(Subsignal("cmd", Pins(cmd, dir="o", assert_width=1)))
+
+    io_1bit = list(io_native)
+    io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", assert_width=1)))
+    if dat3 is not None: # works as electronic card detect
+        io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", assert_width=1)))
+    resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
+                                     name_suffix="1bit"))
+
+    if dat1 is not None and dat2 is not None and dat3 is not None:
+        io_4bit = list(io_native)
+        io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
+                                             assert_width=4)))
+        resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
+                                         name_suffix="4bit"))
+
+    if dat3 is not None:
+        io_spi = list(io_common)
+        io_spi.append(Subsignal("cs", PinsN(dat3, dir="io"))) # doubles as electronic card detect
+        io_spi.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
+        io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", assert_width=1)))
+        io_spi.append(Subsignal("miso", Pins(dat0, dir="i", assert_width=1)))
+        resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
+                                         name_suffix="spi"))
+
+    return resources
+
+
+def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
+    io = []
+    io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
+    if oe is not None:
+        # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
+        io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
+    io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
+    io.append(Subsignal("a", Pins(a, dir="o")))
+    io.append(Subsignal("d", Pins(d, dir="io")))
+    if dm is not None:
+        io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
+    if attrs is not None:
+        io.append(attrs)
+    return Resource.family(*args, default_name="sram", ios=io)

diff --git a/nmigen_boards/resources/user.py b/nmigen_boards/resources/user.py
new file mode 100644 (file)
index 0000000..8faa736
--- /dev/null
+++ b/nmigen_boards/resources/user.py
@@ -0,0 +1,43 @@
+from nmigen.build import *
+
+
+__all__ = ["LEDResources", "RGBLEDResource", "ButtonResources", "SwitchResources"]
+
+
+def _SplitResources(*args, pins, invert=False, attrs=None, default_name, dir):
+    assert isinstance(pins, (str, list, dict))
+
+    if isinstance(pins, str):
+        pins = pins.split()
+    if isinstance(pins, list):
+        pins = dict(enumerate(pins))
+
+    resources = []
+    for number, pin in pins.items():
+        ios = [Pins(pin, dir=dir, invert=invert)]
+        if attrs is not None:
+            ios.append(attrs)
+        resources.append(Resource.family(*args, number, default_name=default_name, ios=ios))
+    return resources
+
+
+def LEDResources(*args, **kwargs):
+    return _SplitResources(*args, **kwargs, default_name="led", dir="o")
+
+
+def RGBLEDResource(*args, r, g, b, invert=False, attrs=None):
+    ios = []
+    ios.append(Subsignal("r", Pins(r, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
+    ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
+    if attrs is not None:
+        ios.append(attrs)
+    return Resource.family(*args, default_name="rgb_led", ios=ios)
+
+
+def ButtonResources(*args, **kwargs):
+    return _SplitResources(*args, **kwargs, default_name="button", dir="i")
+
+
+def SwitchResources(*args, **kwargs):
+    return _SplitResources(*args, **kwargs, default_name="switch", dir="i")

diff --git a/nmigen_boards/sk_xc6slx9.py b/nmigen_boards/sk_xc6slx9.py
index ced857a1a20a76851fd684b4ef7dd8e4dbdbab5b..cec6d2f1d5f3fd38b96c7b828e6745f9057132fb 100644 (file)
--- a/nmigen_boards/sk_xc6slx9.py
+++ b/nmigen_boards/sk_xc6slx9.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.xilinx_spartan_3_6 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["SK_XC6SLX9Platform"]

diff --git a/nmigen_boards/tinyfpga_bx.py b/nmigen_boards/tinyfpga_bx.py
index 537d0fe9f7909ae75687277b529f29537d5aebc2..75de676f01290dd324117a18432dc1aaf832314f 100644 (file)
--- a/nmigen_boards/tinyfpga_bx.py
+++ b/nmigen_boards/tinyfpga_bx.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ice40 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["TinyFPGABXPlatform"]

diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index a3890ac13404cfd873cead6404461e12a97b232f..4847d9a58ad5b5e04783cc29a145354347402386 100644 (file)
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -3,7 +3,7 @@ import subprocess
 
 from nmigen.build import *
 from nmigen.vendor.lattice_ecp5 import *
-from .dev import *
+from .resources import *
 
 
 __all__ = ["VersaECP5Platform"]