src/bsv/peripheral_gen/base.py

   1 import types
   2
   3
   4 def li(txt, indent):
   5     indent = ' ' * indent
   6     istxt = False
   7     if isinstance(txt, str):
   8         istxt = True
   9         txt = txt.split('\n')
  10     res = []
  11     for line in txt:
  12         line = line.split('\n')
  13         res += line
  14     txt = res
  15     res = []
  16     for line in txt:
  17         res.append(indent + line)
  18     if istxt:
  19         res = '\n'.join(res)
  20     return res
  21
  22
  23 class PBase(object):
  24     def __init__(self, name):
  25         self.name = name
  26
  27     def extifdecl(self, name, count):
  28         sname = self.get_iname(count)
  29         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  30
  31     def has_axi_master(self):
  32         return False
  33
  34     def irq_name(self):
  35         return ""
  36
  37     def mk_dma_irq(self, name, count):
  38         if not self.irq_name():
  39             return ''
  40         sname = self.get_iname(count)
  41         return "{0}_interrupt".format(sname)
  42
  43     def mk_dma_rule(self, name, count):
  44         irqname = self.mk_dma_irq(name, count)
  45         if not irqname:
  46             return ''
  47         pirqname = self.irq_name().format(count)
  48         template = "   {0}_interrupt.send(\n" + \
  49                    "           slow_peripherals.{1});"
  50         return template.format(irqname, pirqname)
  51
  52     def get_clock_reset(self, name, count):
  53         return "slow_clock,slow_reset"
  54
  55     def mk_dma_sync(self, name, count):
  56         irqname = self.mk_dma_irq(name, count)
  57         if not irqname:
  58             return ''
  59         sname = self.peripheral.iname().format(count)
  60         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  61                    "           <-mkSyncBitToCC({1});"
  62         return template.format(irqname, self.get_clock_reset(name, count))
  63
  64     def mk_dma_connect(self, name, count):
  65         irqname = self.mk_dma_irq(name, count)
  66         if not irqname:
  67             return ''
  68         return "{0}.read".format(irqname)
  69
  70     def fastifdecl(self, name, count):
  71         return ''
  72
  73     def slowifdeclmux(self, name, count):
  74         return ''
  75
  76     def slowimport(self):
  77         return ''
  78
  79     def num_axi_regs32(self):
  80         return 0
  81
  82     def slowifdecl(self):
  83         return ''
  84
  85     def get_iname(self, inum):
  86         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  87
  88     def axibase(self, name, ifacenum):
  89         name = name.upper()
  90         return "%(name)s%(ifacenum)dBase" % locals()
  91
  92     def axiend(self, name, ifacenum):
  93         name = name.upper()
  94         return "%(name)s%(ifacenum)dEnd" % locals()
  95
  96     def axi_reg_def(self, start, name, ifacenum):
  97         name = name.upper()
  98         offs = self.num_axi_regs32() * 4 * 16
  99         if offs == 0:
 100             return ('', 0)
 101         end = start + offs - 1
 102         bname = self.axibase(name, ifacenum)
 103         bend = self.axiend(name, ifacenum)
 104         comment = "%d 32-bit regs" % self.num_axi_regs32()
 105         return ("    `define %(bname)s 'h%(start)08X\n"
 106                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 107                 offs)
 108
 109     def axi_master_name(self, name, ifacenum, typ=''):
 110         name = name.upper()
 111         return "{0}{1}_master_num".format(name, ifacenum)
 112
 113     def axi_slave_name(self, name, ifacenum, typ=''):
 114         name = name.upper()
 115         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 116
 117     def axi_master_idx(self, idx, name, ifacenum, typ):
 118         name = self.axi_master_name(name, ifacenum, typ)
 119         return ("typedef {0} {1};".format(idx, name), 1)
 120
 121     def axi_slave_idx(self, idx, name, ifacenum, typ):
 122         name = self.axi_slave_name(name, ifacenum, typ)
 123         return ("typedef {0} {1};".format(idx, name), 1)
 124
 125     def axi_addr_map(self, name, ifacenum):
 126         bname = self.axibase(name, ifacenum)
 127         bend = self.axiend(name, ifacenum)
 128         name = self.axi_slave_name(name, ifacenum)
 129         template = """\
 130 if(addr>=`{0} && addr<=`{1})
 131     return tuple2(True,fromInteger(valueOf({2})));
 132 else"""
 133         return template.format(bname, bend, name)
 134
 135     def mk_pincon(self, name, count):
 136         # TODO: really should be using bsv.interface_decl.Interfaces
 137         # pin-naming rules.... logic here is hard-coded to duplicate
 138         # it (see Interface.__init__ outen)
 139         ret = []
 140         for p in self.peripheral.pinspecs:
 141             typ = p['type']
 142             pname = p['name']
 143             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 144             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 145             ret.append("//%s %s" % (n, str(p)))
 146             sname = self.peripheral.iname().format(count)
 147             sname = "{0}.{1}".format(sname, pname)
 148             ps = "pinmux.peripheral_side.%s" % sname
 149             if typ == 'out' or typ == 'inout':
 150                 fname = self.pinname_out(pname)
 151                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 152                     n_ = "{0}{1}".format(n, count)
 153                 else:
 154                     n_ = n
 155                 if fname:
 156                     if p.get('outen'):
 157                         ps_ = ps + '_out'
 158                     else:
 159                         ps_ = ps
 160                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 161                                .format(ps_, n_, fname))
 162                 fname = None
 163                 if p.get('outen'):
 164                     fname = self.pinname_outen(pname)
 165                 if fname:
 166                     if isinstance(fname, str):
 167                         fname = "{0}.{1}".format(n_, fname)
 168                     fname = self.pinname_tweak(pname, 'outen', fname)
 169                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 170                                .format(ps, fname))
 171             if typ == 'in' or typ == 'inout':
 172                 fname = self.pinname_in(pname)
 173                 if fname:
 174                     if p.get('outen'):
 175                         ps_ = ps + '_in'
 176                     else:
 177                         ps_ = ps
 178                     n_ = "{0}{1}".format(n, count)
 179                     n_ = '{0}.{1}'.format(n_, fname)
 180                     n_ = self.ifname_tweak(pname, 'in', n_)
 181                     ret.append("mkConnection({1},\n\t\t\t{0});".format(ps_, n_))
 182         return '\n'.join(ret)
 183
 184     def mk_cellconn(self, *args):
 185         return ''
 186
 187     def mkfast_peripheral(self, size=0):
 188         return ''
 189
 190     def mkslow_peripheral(self, size=0):
 191         return ''
 192
 193     def mksuffix(self, name, i):
 194         return i
 195
 196     def __mk_connection(self, con, aname, fabricname):
 197         txt = "mkConnection ({2}.v_to_slaves\n" + \
 198               "            [fromInteger(valueOf({1}))],\n" + \
 199               "            {0});"
 200
 201         print "PBase __mk_connection", self.name, aname
 202         if not con:
 203             return ''
 204         return txt.format(con, aname, fabricname)
 205
 206     def __mk_master_connection(self, con, aname):
 207         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 208               "            [fromInteger(valueOf({1}))],\n" + \
 209               "            {0});"
 210
 211         print "PBase __mk_connection", self.name, aname
 212         if not con:
 213             return ''
 214         return txt.format(con, aname)
 215
 216     def mk_connection(self, count, fabricname, typ, name=None):
 217         if name is None:
 218             name = self.name
 219         print "PBase mk_conn", self.name, count
 220         aname = self.axi_slave_name(name, count, typ)
 221         #dname = self.mksuffix(name, count)
 222         #dname = "{0}{1}".format(name, dname)
 223         con = self._mk_connection(name, count).format(count, aname)
 224         return self.__mk_connection(con, aname, fabricname)
 225
 226     def _mk_connection(self, name=None, count=0):
 227         return ''
 228
 229     def pinname_out(self, pname):
 230         return ''
 231
 232     def pinname_in(self, pname):
 233         return ''
 234
 235     def pinname_outen(self, pname):
 236         return ''
 237
 238     def ifname_tweak(self, pname, typ, txt):
 239         return txt
 240
 241     def pinname_tweak(self, pname, typ, txt):
 242         return txt
 243
 244     def num_irqs(self):
 245         return 0
 246
 247     def mk_plic(self, inum, irq_offs):
 248         res = []
 249         print "mk_plic", self.name, inum, irq_offs
 250         niq = self.num_irqs()
 251         if niq == 0:
 252             return ('', irq_offs)
 253         name = self.get_iname(inum)
 254         res.append("// PLIC rules for {0}".format(name))
 255         for idx in range(niq):
 256             plic_obj = self.plic_object(name, idx)
 257             print "plic_obj", name, idx, plic_obj
 258             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 259             res.append(plic)
 260             irq_offs += 1  # increment to next irq
 261         return ('\n'.join(res), irq_offs)
 262
 263     def mk_ext_ifacedef(self, iname, inum):
 264         return ''
 265
 266     def extfastifinstance(self, name, count):
 267         return ''
 268
 269     def _extifinstance(self, name, count, suffix, prefix, samename=False):
 270         pname = self.get_iname(count)
 271         if samename:
 272             sname = pname
 273         else:
 274             sname = self.peripheral.iname().format(count)
 275         template = "interface {0}{3} = {2}{1};"
 276         return template.format(pname, sname, prefix, suffix)
 277
 278     def extifinstance2(self, name, count):
 279         return ''
 280
 281     def extifinstance(self, name, count):
 282         return self._extifinstance(name, count, "",
 283                                    "pinmux.peripheral_side.")
 284
 285
 286 mkplic_rule = """\
 287 rule rl_connect_{0}_to_plic_{2};
 288    if({1} == 1'b1) begin
 289        ff_gateway_queue[{2}].enq(1);
 290        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 291    end
 292 endrule
 293 """
 294
 295 axi_master_declarations = """\
 296 typedef 0 Dmem_master_num;
 297 typedef 1 Imem_master_num;
 298 {0}
 299 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 300                 Debug_master_num;
 301 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 302                 DMA_master_num;
 303 typedef TAdd#(DMA_master_num,1)
 304                 Num_Masters;
 305 """
 306
 307 axi_fastslave_declarations = """\
 308 {0}
 309 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
 310 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 311                       Sdram_cfg_slave_num;
 312 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 313                 BootRom_slave_num   ;
 314 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 315                 Debug_slave_num ;
 316 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 317                 TCM_slave_num;
 318 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
 319                 Dma_slave_num;
 320 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 321 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 322                 VME_slave_num;
 323 typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
 324                 FlexBus_slave_num;
 325 typedef TAdd#(FlexBus_slave_num,1)
 326                 Num_Slaves;
 327
 328 """
 329
 330 axi_slave_declarations = """\
 331 typedef  0  SlowMaster;
 332 {0}
 333 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 334               CLINT_slave_num;
 335 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 336               Plic_slave_num;
 337 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 338               AxiExp1_slave_num;
 339 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 340 """
 341
 342 pinmux_cellrule = """\
 343 rule connect_select_lines_pinmux;
 344 {0}
 345 endrule
 346 """
 347
 348
 349 class CallFn(object):
 350     def __init__(self, peripheral, name):
 351         self.peripheral = peripheral
 352         self.name = name
 353
 354     def __call__(self, *args):
 355         #print "__call__", self.name, self.peripheral.slow, args
 356         if not self.peripheral.slow:
 357             return ''
 358         return getattr(self.peripheral.slow, self.name)(*args[1:])
 359
 360
 361 class PeripheralIface(object):
 362     def __init__(self, ifacename):
 363         self.slow = None
 364         slow = slowfactory.getcls(ifacename)
 365         print "Iface", ifacename, slow
 366         if slow:
 367             self.slow = slow(ifacename)
 368             self.slow.peripheral = self
 369         for fname in ['slowimport',
 370                       'extfastifinstance',
 371                       'extifinstance2', 'extifinstance', 'extifdecl',
 372                       'slowifdecl', 'slowifdeclmux',
 373                       'fastifdecl',
 374                       'mkslow_peripheral',
 375                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 376                       'mkfast_peripheral',
 377                       'mk_plic', 'mk_ext_ifacedef',
 378                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 379             fn = CallFn(self, fname)
 380             setattr(self, fname, types.MethodType(fn, self))
 381
 382         #print "PeripheralIface"
 383         #print dir(self)
 384
 385     def mksuffix(self, name, i):
 386         if self.slow is None:
 387             return i
 388         return self.slow.mksuffix(name, i)
 389
 390     def axi_reg_def(self, start, count):
 391         if not self.slow:
 392             return ('', 0)
 393         return self.slow.axi_reg_def(start, self.ifacename, count)
 394
 395     def axi_master_idx(self, start, count, typ):
 396         if not self.slow or not self.slow.has_axi_master():
 397             return ('', 0)
 398         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 399
 400     def axi_slave_idx(self, start, count, typ):
 401         if not self.slow:
 402             return ('', 0)
 403         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 404
 405     def axi_addr_map(self, count):
 406         if not self.slow:
 407             return ''
 408         return self.slow.axi_addr_map(self.ifacename, count)
 409
 410
 411 class PeripheralInterfaces(object):
 412     def __init__(self):
 413         self.fastbusmode = False
 414
 415     def slowimport(self, *args):
 416         ret = []
 417         for (name, count) in self.ifacecount:
 418             #print "slowimport", name, self.data[name].slowimport
 419             ret.append(self.data[name].slowimport())
 420         return '\n'.join(li(list(filter(None, ret)), 4))
 421
 422     def extfastifinstance(self, *args):
 423         ret = []
 424         for (name, count) in self.ifacecount:
 425             for i in range(count):
 426                 iname = self.data[name].iname().format(i)
 427                 print "extfast", iname, self.is_on_fastbus(name, i)
 428                 if self.is_on_fastbus(name, i):
 429                     continue
 430                 ret.append(self.data[name].extfastifinstance(name, i))
 431         return '\n'.join(li(list(filter(None, ret)), 8))
 432
 433     def extifinstance2(self, *args):
 434         ret = []
 435         for (name, count) in self.ifacecount:
 436             for i in range(count):
 437                 iname = self.data[name].iname().format(i)
 438                 ret.append(self.data[name].extifinstance2(name, i))
 439         return '\n'.join(li(list(filter(None, ret)), 8))
 440
 441     def extifinstance(self, *args):
 442         ret = []
 443         for (name, count) in self.ifacecount:
 444             for i in range(count):
 445                 iname = self.data[name].iname().format(i)
 446                 if not self.is_on_fastbus(name, i):
 447                     continue
 448                 ret.append(self.data[name].extifinstance(name, i))
 449         return '\n'.join(li(list(filter(None, ret)), 8))
 450
 451     def extifdecl(self, *args):
 452         ret = []
 453         for (name, count) in self.ifacecount:
 454             for i in range(count):
 455                 if not self.is_on_fastbus(name, i):
 456                     continue
 457                 ret.append(self.data[name].extifdecl(name, i))
 458         return '\n'.join(li(list(filter(None, ret)), 8))
 459
 460     def slowifdeclmux(self, *args):
 461         ret = []
 462         for (name, count) in self.ifacecount:
 463             for i in range(count):
 464                 ret.append(self.data[name].slowifdeclmux(name, i))
 465         return '\n'.join(li(list(filter(None, ret)), 8))
 466
 467     def fastifdecl(self, *args):
 468         ret = []
 469         for (name, count) in self.ifacecount:
 470             for i in range(count):
 471                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 472                 if self.is_on_fastbus(name, i):
 473                     continue
 474                 ret.append(self.data[name].fastifdecl(name, i))
 475         return '\n'.join(li(list(filter(None, ret)), 4))
 476
 477     def slowifdecl(self, *args):
 478         ret = []
 479         for (name, count) in self.ifacecount:
 480             for i in range(count):
 481                 if self.is_on_fastbus(name, i):
 482                     continue
 483                 ret.append(self.data[name].slowifdecl().format(i, name))
 484         return '\n'.join(list(filter(None, ret)))
 485
 486     def axi_reg_def(self, *args):
 487         ret = []
 488         start = 0x00011100  # start of AXI peripherals address
 489         for (name, count) in self.ifacecount:
 490             for i in range(count):
 491                 if self.is_on_fastbus(name, i):
 492                     continue
 493                 x = self.data[name].axi_reg_def(start, i)
 494                 #print ("ifc", name, x)
 495                 (rdef, offs) = x
 496                 ret.append(rdef)
 497                 start += offs
 498         return '\n'.join(list(filter(None, ret)))
 499
 500     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 501         ret = []
 502         for (name, count) in self.ifacecount:
 503             for i in range(count):
 504                 if self.is_on_fastbus(name, i):
 505                     continue
 506                 if typ == 'master':
 507                     fn = self.data[name].axi_master_idx
 508                 else:
 509                     fn = self.data[name].axi_slave_idx
 510                 (rdef, offs) = fn(start, i, idxtype)
 511                 #print ("ifc", name, rdef, offs)
 512                 ret.append(rdef)
 513                 start += offs
 514         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 515         decls = '\n'.join(list(filter(None, ret)))
 516         return template.format(decls)
 517
 518     def axi_slave_idx(self, *args):
 519         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 520                                  '', *args)
 521
 522     def axi_fastslave_idx(self, *args):
 523         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 524                                  'fast', *args)
 525
 526     def axi_master_idx(self, *args):
 527         return self._axi_num_idx(2, axi_master_declarations, 'master',
 528                                  'master', *args)
 529
 530     def axi_fastslave_idx(self, *args):
 531         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 532                                  'fast', *args)
 533
 534     def axi_addr_map(self, *args):
 535         ret = []
 536         for (name, count) in self.ifacecount:
 537             for i in range(count):
 538                 if self.is_on_fastbus(name, i):
 539                     continue
 540                 ret.append(self.data[name].axi_addr_map(i))
 541         return '\n'.join(li(list(filter(None, ret)), 8))
 542
 543     def mkfast_peripheral(self, *args):
 544         ret = []
 545         for (name, count) in self.ifacecount:
 546             for i in range(count):
 547                 if self.is_on_fastbus(name, i):
 548                     continue
 549                 #print "mkfast", name, count
 550                 x = self.data[name].mkfast_peripheral()
 551                 print name, count, x
 552                 suffix = self.data[name].mksuffix(name, i)
 553                 ret.append(x.format(suffix))
 554         return '\n'.join(li(list(filter(None, ret)), 8))
 555
 556     def mkslow_peripheral(self, *args):
 557         ret = []
 558         for (name, count) in self.ifacecount:
 559             for i in range(count):
 560                 if self.is_on_fastbus(name, i):
 561                     continue
 562                 #print "mkslow", name, count
 563                 x = self.data[name].mkslow_peripheral()
 564                 print name, count, x
 565                 suffix = self.data[name].mksuffix(name, i)
 566                 ret.append(x.format(suffix))
 567         return '\n'.join(li(list(filter(None, ret)), 8))
 568
 569     def mk_fast_connection(self, *args):
 570         ret = []
 571         for (name, count) in self.ifacecount:
 572             for i in range(count):
 573                 if self.is_on_fastbus(name, i):
 574                     continue
 575                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 576                 if name == 'gpioa':
 577                     print "txt", txt
 578                     print self.data[name].mk_connection
 579                 ret.append(txt)
 580         return '\n'.join(li(list(filter(None, ret)), 12))
 581
 582     def mk_connection(self, *args):
 583         ret = []
 584         for (name, count) in self.ifacecount:
 585             for i in range(count):
 586                 if self.is_on_fastbus(name, i):
 587                     continue
 588                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 589                 if name == 'gpioa':
 590                     print "txt", txt
 591                     print self.data[name].mk_connection
 592                 ret.append(txt)
 593         return '\n'.join(li(list(filter(None, ret)), 8))
 594
 595     def mk_cellconn(self):
 596         ret = []
 597         cellcount = 0
 598         for (name, count) in self.ifacecount:
 599             for i in range(count):
 600                 if self.is_on_fastbus(name, i):
 601                     continue
 602                 res = self.data[name].mk_cellconn(cellcount, name, i)
 603                 if not res:
 604                     continue
 605                 (txt, cellcount) = res
 606                 ret.append(txt)
 607         ret = li('\n'.join(list(filter(None, ret))), 4)
 608         return li(pinmux_cellrule.format(ret), 4)
 609
 610     def mk_pincon(self):
 611         ret = []
 612         for (name, count) in self.ifacecount:
 613             for i in range(count):
 614                 if self.is_on_fastbus(name, i):
 615                     continue
 616                 txt = self.data[name].mk_pincon(name, i)
 617                 ret.append(txt)
 618         return '\n'.join(li(list(filter(None, ret)), 4))
 619
 620     def mk_dma_irq(self):
 621         ret = []
 622         sync = []
 623         rules = []
 624         cnct = []
 625
 626         self.dma_count = 0
 627
 628         for (name, count) in self.ifacecount:
 629             ifacerules = []
 630             for i in range(count):
 631                 if not self.is_on_fastbus(name, i):
 632                     continue
 633                 txt = self.data[name].mk_dma_sync(name, i)
 634                 if txt:
 635                     self.dma_count += 1
 636                 sync.append(txt)
 637                 txt = self.data[name].mk_dma_rule(name, i)
 638                 ifacerules.append(txt)
 639                 txt = self.data[name].mk_dma_connect(name, i)
 640                 cnct.append(txt)
 641             ifacerules = list(filter(None, ifacerules))
 642             if ifacerules:
 643                 txt = "rule synchronize_%s_interrupts;" % name
 644                 rules.append(txt)
 645                 rules += ifacerules
 646                 rules.append("endrule")
 647
 648         cnct = list(filter(None, cnct))
 649         ct = self.dma_count
 650         _cnct = ["rule rl_connect_interrupt_to_DMA;",
 651                  "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 652         spc = "                      "
 653         spcsep = ",\n" + spc
 654         cnct = _cnct + [spc + spcsep.join(cnct)]
 655         cnct.append("   };")
 656         cnct.append("   dma.interrupt_from_peripherals(\n" +
 657                     "       lv_interrupt_to_DMA);")
 658         cnct.append("endrule;")
 659
 660         ret = list(filter(None, sync + rules + cnct))
 661         ret = li(ret, 15)
 662         return '\n'.join(ret)
 663
 664     def num_dmachannels(self):
 665         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 666
 667     def mk_ext_ifacedef(self):
 668         ret = []
 669         for (name, count) in self.ifacecount:
 670             for i in range(count):
 671                 if self.is_on_fastbus(name, i):
 672                     continue
 673                 txt = self.data[name].mk_ext_ifacedef(name, i)
 674                 ret.append(txt)
 675         return '\n'.join(li(list(filter(None, ret)), 8))
 676
 677     def mk_plic(self):
 678         ret = []
 679         irq_offs = 8  # XXX: DMA scovers 0-7?
 680         for (name, count) in self.ifacecount:
 681             for i in range(count):
 682                 if self.is_on_fastbus(name, i):
 683                     continue
 684                 res = self.data[name].mk_plic(i, irq_offs)
 685                 if not res:
 686                     continue
 687                 (txt, irq_offs) = res
 688                 ret.append(txt)
 689         self.num_slow_irqs = irq_offs
 690         return '\n'.join(li(list(filter(None, ret)), 4))
 691
 692     def mk_sloirqsdef(self):
 693         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 694
 695     def is_on_fastbus(self, name, i):
 696         #print "fastbus mode", self.fastbusmode, name, i
 697         iname = self.data[name].iname().format(i)
 698         if self.fastbusmode:
 699             return iname not in self.fastbus
 700         return iname in self.fastbus
 701
 702
 703 class PFactory(object):
 704     def getcls(self, name):
 705         from uart import uart
 706         from quart import quart
 707         from sdmmc import sdmmc
 708         from pwm import pwm
 709         from eint import eint
 710         from rs232 import rs232
 711         from twi import twi
 712         from eint import eint
 713         from jtag import jtag
 714         from spi import spi, mspi
 715         from qspi import qspi, mqspi
 716         from gpio import gpio
 717         from rgbttl import rgbttl
 718
 719         for k, v in {'uart': uart,
 720                      'rs232': rs232,
 721                      'twi': twi,
 722                      'quart': quart,
 723                      'mqspi': mqspi,
 724                      'mspi': mspi,
 725                      'qspi': qspi,
 726                      'spi': spi,
 727                      'pwm': pwm,
 728                      'eint': eint,
 729                      'sd': sdmmc,
 730                      'jtag': jtag,
 731                      'lcd': rgbttl,
 732                      'gpio': gpio
 733                      }.items():
 734             if name.startswith(k):
 735                 return v
 736         return None
 737
 738
 739 slowfactory = PFactory()
 740
 741 if __name__ == '__main__':
 742     p = uart('uart')
 743     print p.slowimport()
 744     print p.slowifdecl()
 745     i = PeripheralIface('uart')
 746     print i, i.slow
 747     i = PeripheralIface('gpioa')
 748     print i, i.slow