src/bsv/peripheral_gen/base.py

   1 import types
   2
   3
   4 def li(txt, indent):
   5     indent = ' ' * indent
   6     istxt = False
   7     if isinstance(txt, str):
   8         istxt = True
   9         txt = txt.split('\n')
  10     res = []
  11     for line in txt:
  12         line = line.split('\n')
  13         res += line
  14     txt = res
  15     res = []
  16     for line in txt:
  17         res.append(indent + line)
  18     if istxt:
  19         res = '\n'.join(res)
  20     return res
  21
  22
  23 class PBase(object):
  24     def __init__(self, name):
  25         self.name = name
  26
  27     def extifdecl(self, name, count):
  28         sname = self.get_iname(count)
  29         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  30
  31     def has_axi_master(self):
  32         return False
  33
  34     def irq_name(self):
  35         return ""
  36
  37     def mk_dma_irq(self, name, count):
  38         if not self.irq_name():
  39             return ''
  40         sname = self.get_iname(count)
  41         return "{0}_interrupt".format(sname)
  42
  43     def mk_dma_rule(self, name, count):
  44         irqname = self.mk_dma_irq(name, count)
  45         if not irqname:
  46             return ''
  47         pirqname = self.irq_name().format(count)
  48         template = "   {0}_interrupt.send(\n" + \
  49                    "           slow_peripherals.{1});"
  50         return template.format(irqname, pirqname)
  51
  52     def get_clock_reset(self, name, count):
  53         return "slow_clock,slow_reset"
  54
  55     def mk_dma_sync(self, name, count):
  56         irqname = self.mk_dma_irq(name, count)
  57         if not irqname:
  58             return ''
  59         sname = self.peripheral.iname().format(count)
  60         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  61                    "           <-mkSyncBitToCC({1});"
  62         return template.format(irqname, self.get_clock_reset(name, count))
  63
  64     def mk_dma_connect(self, name, count):
  65         irqname = self.mk_dma_irq(name, count)
  66         if not irqname:
  67             return ''
  68         return "{0}.read".format(irqname)
  69
  70     def fastifdecl(self, name, count):
  71         return ''
  72
  73     def slowifdeclmux(self, name, count):
  74         return ''
  75
  76     def slowimport(self):
  77         return ''
  78
  79     def num_axi_regs32(self):
  80         return 0
  81
  82     def slowifdecl(self):
  83         return ''
  84
  85     def get_iname(self, inum):
  86         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  87
  88     def axibase(self, name, ifacenum):
  89         name = name.upper()
  90         return "%(name)s%(ifacenum)dBase" % locals()
  91
  92     def axiend(self, name, ifacenum):
  93         name = name.upper()
  94         return "%(name)s%(ifacenum)dEnd" % locals()
  95
  96     def axi_reg_def(self, start, name, ifacenum):
  97         name = name.upper()
  98         offs = self.num_axi_regs32() * 4 * 16
  99         if offs == 0:
 100             return ('', 0)
 101         end = start + offs - 1
 102         bname = self.axibase(name, ifacenum)
 103         bend = self.axiend(name, ifacenum)
 104         comment = "%d 32-bit regs" % self.num_axi_regs32()
 105         return ("    `define %(bname)s 'h%(start)08X\n"
 106                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 107                 offs)
 108
 109     def axi_master_name(self, name, ifacenum, typ=''):
 110         name = name.upper()
 111         return "{0}{1}_master_num".format(name, ifacenum)
 112
 113     def axi_slave_name(self, name, ifacenum, typ=''):
 114         name = name.upper()
 115         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 116
 117     def axi_master_idx(self, idx, name, ifacenum, typ):
 118         name = self.axi_master_name(name, ifacenum, typ)
 119         return ("typedef {0} {1};".format(idx, name), 1)
 120
 121     def axi_slave_idx(self, idx, name, ifacenum, typ):
 122         name = self.axi_slave_name(name, ifacenum, typ)
 123         return ("typedef {0} {1};".format(idx, name), 1)
 124
 125     def axi_addr_map(self, name, ifacenum):
 126         bname = self.axibase(name, ifacenum)
 127         bend = self.axiend(name, ifacenum)
 128         name = self.axi_slave_name(name, ifacenum)
 129         template = """\
 130 if(addr>=`{0} && addr<=`{1})
 131     return tuple2(True,fromInteger(valueOf({2})));
 132 else"""
 133         return template.format(bname, bend, name)
 134
 135     def mk_pincon(self, name, count):
 136         # TODO: really should be using bsv.interface_decl.Interfaces
 137         # pin-naming rules.... logic here is hard-coded to duplicate
 138         # it (see Interface.__init__ outen)
 139         ret = []
 140         for p in self.peripheral.pinspecs:
 141             typ = p['type']
 142             pname = p['name']
 143             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 144             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 145             ret.append("//%s %s" % (n, str(p)))
 146             sname = self.peripheral.iname().format(count)
 147             sname = "{0}.{1}".format(sname, pname)
 148             ps = "pinmux.peripheral_side.%s" % sname
 149             if typ == 'out' or typ == 'inout':
 150                 fname = self.pinname_out(pname)
 151                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 152                     n_ = "{0}{1}".format(n, count)
 153                 else:
 154                     n_ = n
 155                 if fname:
 156                     if p.get('outen'):
 157                         ps_ = ps + '_out'
 158                     else:
 159                         ps_ = ps
 160                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 161                                .format(ps_, n_, fname))
 162                 fname = None
 163                 if p.get('outen'):
 164                     fname = self.pinname_outen(pname)
 165                 if fname:
 166                     if isinstance(fname, str):
 167                         fname = "{0}.{1}".format(n_, fname)
 168                     fname = self.pinname_tweak(pname, 'outen', fname)
 169                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 170                                .format(ps, fname))
 171             if typ == 'in' or typ == 'inout':
 172                 fname = self.pinname_in(pname)
 173                 if fname:
 174                     if p.get('outen'):
 175                         ps_ = ps + '_in'
 176                     else:
 177                         ps_ = ps
 178                     n_ = "{0}{1}".format(n, count)
 179                     n_ = '{0}.{1}'.format(n_, fname)
 180                     n_ = self.ifname_tweak(pname, 'in', n_)
 181                     ret.append(
 182                         "mkConnection({1},\n\t\t\t{0});".format(
 183                             ps_, n_))
 184         return '\n'.join(ret)
 185
 186     def mk_cellconn(self, *args):
 187         return ''
 188
 189     def mkfast_peripheral(self, size=0):
 190         return ''
 191
 192     def mkslow_peripheral(self, size=0):
 193         return ''
 194
 195     def mksuffix(self, name, i):
 196         return i
 197
 198     def __mk_connection(self, con, aname, fabricname):
 199         txt = "mkConnection ({2}.v_to_slaves\n" + \
 200               "            [fromInteger(valueOf({1}))],\n" + \
 201               "            {0});"
 202
 203         print "PBase __mk_connection", self.name, aname
 204         if not con:
 205             return ''
 206         return txt.format(con, aname, fabricname)
 207
 208     def __mk_master_connection(self, con, aname):
 209         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 210               "            [fromInteger(valueOf({1}))],\n" + \
 211               "            {0});"
 212
 213         print "PBase __mk_connection", self.name, aname
 214         if not con:
 215             return ''
 216         return txt.format(con, aname)
 217
 218     def mk_connection(self, count, fabricname, typ, name=None):
 219         if name is None:
 220             name = self.name
 221         print "PBase mk_conn", self.name, count
 222         aname = self.axi_slave_name(name, count, typ)
 223         #dname = self.mksuffix(name, count)
 224         #dname = "{0}{1}".format(name, dname)
 225         con = self._mk_connection(name, count).format(count, aname)
 226         return self.__mk_connection(con, aname, fabricname)
 227
 228     def _mk_connection(self, name=None, count=0):
 229         return ''
 230
 231     def pinname_out(self, pname):
 232         return ''
 233
 234     def pinname_in(self, pname):
 235         return ''
 236
 237     def pinname_outen(self, pname):
 238         return ''
 239
 240     def ifname_tweak(self, pname, typ, txt):
 241         return txt
 242
 243     def pinname_tweak(self, pname, typ, txt):
 244         return txt
 245
 246     def num_irqs(self):
 247         return 0
 248
 249     def mk_plic(self, inum, irq_offs):
 250         res = []
 251         print "mk_plic", self.name, inum, irq_offs
 252         niq = self.num_irqs()
 253         if niq == 0:
 254             return ('', irq_offs)
 255         name = self.get_iname(inum)
 256         res.append("// PLIC rules for {0}".format(name))
 257         for idx in range(niq):
 258             plic_obj = self.plic_object(name, idx)
 259             print "plic_obj", name, idx, plic_obj
 260             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 261             res.append(plic)
 262             irq_offs += 1  # increment to next irq
 263         return ('\n'.join(res), irq_offs)
 264
 265     def mk_ext_ifacedef(self, iname, inum):
 266         return ''
 267
 268     def extfastifinstance(self, name, count):
 269         return ''
 270
 271     def _extifinstance(self, name, count, suffix, prefix, samename=False,
 272                        ifsuffix=None):
 273         if ifsuffix is None:
 274             ifsuffix = ''
 275         pname = self.get_iname(count)
 276         if samename:
 277             sname = pname
 278         else:
 279             sname = self.peripheral.iname().format(count)
 280         template = "interface {0}{3} = {2}{1}{4};"
 281         return template.format(pname, sname, prefix, suffix, ifsuffix)
 282
 283     def extifinstance2(self, name, count):
 284         return ''
 285
 286     def extifinstance(self, name, count):
 287         return self._extifinstance(name, count, "",
 288                                    "pinmux.peripheral_side.")
 289
 290
 291 mkplic_rule = """\
 292 rule rl_connect_{0}_to_plic_{2};
 293    if({1} == 1'b1) begin
 294        ff_gateway_queue[{2}].enq(1);
 295        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 296    end
 297 endrule
 298 """
 299
 300 axi_master_declarations = """\
 301 typedef 0 Dmem_master_num;
 302 typedef 1 Imem_master_num;
 303 {0}
 304 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 305                 Debug_master_num;
 306 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 307                 DMA_master_num;
 308 typedef TAdd#(DMA_master_num,1)
 309                 Num_Masters;
 310 """
 311
 312 axi_fastslave_declarations = """\
 313 {0}
 314 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_slave_num;
 315 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 316                       Sdram_cfg_slave_num;
 317 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 318                 BootRom_slave_num   ;
 319 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 320                 Debug_slave_num ;
 321 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 322                 TCM_slave_num;
 323 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
 324                 Dma_slave_num;
 325 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 326 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 327                 VME_slave_num;
 328 typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
 329                 FlexBus_slave_num;
 330 typedef TAdd#(FlexBus_slave_num,1)
 331                 Num_Slaves;
 332
 333 """
 334
 335 axi_slave_declarations = """\
 336 typedef  0  SlowMaster;
 337 {0}
 338 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 339               CLINT_slave_num;
 340 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 341               Plic_slave_num;
 342 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 343               AxiExp1_slave_num;
 344 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 345 """
 346
 347 pinmux_cellrule = """\
 348 rule connect_select_lines_pinmux;
 349 {0}
 350 endrule
 351 """
 352
 353
 354 class CallFn(object):
 355     def __init__(self, peripheral, name):
 356         self.peripheral = peripheral
 357         self.name = name
 358
 359     def __call__(self, *args):
 360         #print "__call__", self.name, self.peripheral.slow, args
 361         if not self.peripheral.slow:
 362             return ''
 363         return getattr(self.peripheral.slow, self.name)(*args[1:])
 364
 365
 366 class PeripheralIface(object):
 367     def __init__(self, ifacename):
 368         self.slow = None
 369         slow = slowfactory.getcls(ifacename)
 370         print "Iface", ifacename, slow
 371         if slow:
 372             self.slow = slow(ifacename)
 373             self.slow.peripheral = self
 374         for fname in ['slowimport',
 375                       'extfastifinstance',
 376                       'extifinstance2', 'extifinstance', 'extifdecl',
 377                       'slowifdecl', 'slowifdeclmux',
 378                       'fastifdecl',
 379                       'mkslow_peripheral',
 380                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 381                       'mkfast_peripheral',
 382                       'mk_plic', 'mk_ext_ifacedef',
 383                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 384             fn = CallFn(self, fname)
 385             setattr(self, fname, types.MethodType(fn, self))
 386
 387         #print "PeripheralIface"
 388         #print dir(self)
 389
 390     def mksuffix(self, name, i):
 391         if self.slow is None:
 392             return i
 393         return self.slow.mksuffix(name, i)
 394
 395     def axi_reg_def(self, start, count):
 396         if not self.slow:
 397             return ('', 0)
 398         return self.slow.axi_reg_def(start, self.ifacename, count)
 399
 400     def axi_master_idx(self, start, count, typ):
 401         if not self.slow or not self.slow.has_axi_master():
 402             return ('', 0)
 403         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 404
 405     def axi_slave_idx(self, start, count, typ):
 406         if not self.slow:
 407             return ('', 0)
 408         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 409
 410     def axi_addr_map(self, count):
 411         if not self.slow:
 412             return ''
 413         return self.slow.axi_addr_map(self.ifacename, count)
 414
 415
 416 class PeripheralInterfaces(object):
 417     def __init__(self):
 418         self.fastbusmode = False
 419
 420     def slowimport(self, *args):
 421         ret = []
 422         for (name, count) in self.ifacecount:
 423             #print "slowimport", name, self.data[name].slowimport
 424             ret.append(self.data[name].slowimport())
 425         return '\n'.join(li(list(filter(None, ret)), 4))
 426
 427     def extfastifinstance(self, *args):
 428         ret = []
 429         for (name, count) in self.ifacecount:
 430             for i in range(count):
 431                 iname = self.data[name].iname().format(i)
 432                 print "extfast", iname, self.is_on_fastbus(name, i)
 433                 if self.is_on_fastbus(name, i):
 434                     continue
 435                 ret.append(self.data[name].extfastifinstance(name, i))
 436         return '\n'.join(li(list(filter(None, ret)), 8))
 437
 438     def extifinstance2(self, *args):
 439         ret = []
 440         for (name, count) in self.ifacecount:
 441             for i in range(count):
 442                 iname = self.data[name].iname().format(i)
 443                 ret.append(self.data[name].extifinstance2(name, i))
 444         return '\n'.join(li(list(filter(None, ret)), 8))
 445
 446     def extifinstance(self, *args):
 447         ret = []
 448         for (name, count) in self.ifacecount:
 449             for i in range(count):
 450                 iname = self.data[name].iname().format(i)
 451                 if not self.is_on_fastbus(name, i):
 452                     continue
 453                 ret.append(self.data[name].extifinstance(name, i))
 454         return '\n'.join(li(list(filter(None, ret)), 8))
 455
 456     def extifdecl(self, *args):
 457         ret = []
 458         for (name, count) in self.ifacecount:
 459             for i in range(count):
 460                 if not self.is_on_fastbus(name, i):
 461                     continue
 462                 ret.append(self.data[name].extifdecl(name, i))
 463         return '\n'.join(li(list(filter(None, ret)), 8))
 464
 465     def slowifdeclmux(self, *args):
 466         ret = []
 467         for (name, count) in self.ifacecount:
 468             for i in range(count):
 469                 ret.append(self.data[name].slowifdeclmux(name, i))
 470         return '\n'.join(li(list(filter(None, ret)), 8))
 471
 472     def fastifdecl(self, *args):
 473         ret = []
 474         for (name, count) in self.ifacecount:
 475             for i in range(count):
 476                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 477                 if self.is_on_fastbus(name, i):
 478                     continue
 479                 ret.append(self.data[name].fastifdecl(name, i))
 480         return '\n'.join(li(list(filter(None, ret)), 4))
 481
 482     def slowifdecl(self, *args):
 483         ret = []
 484         for (name, count) in self.ifacecount:
 485             for i in range(count):
 486                 if self.is_on_fastbus(name, i):
 487                     continue
 488                 ret.append(self.data[name].slowifdecl().format(i, name))
 489         return '\n'.join(list(filter(None, ret)))
 490
 491     def axi_fastmem_def(self, *args):
 492         return self._axi_reg_def(0x50000000, *args)
 493
 494     def axi_reg_def(self, *args):
 495         return self._axi_reg_def(0x00011100, *args)
 496
 497     def _axi_reg_def(self, start, *args):
 498         ret = []
 499         for (name, count) in self.ifacecount:
 500             for i in range(count):
 501                 if self.is_on_fastbus(name, i):
 502                     continue
 503                 x = self.data[name].axi_reg_def(start, i)
 504                 #print ("ifc", name, x)
 505                 (rdef, offs) = x
 506                 ret.append(rdef)
 507                 start += offs
 508         return '\n'.join(list(filter(None, ret)))
 509
 510     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 511         ret = []
 512         for (name, count) in self.ifacecount:
 513             for i in range(count):
 514                 if self.is_on_fastbus(name, i):
 515                     continue
 516                 if typ == 'master':
 517                     fn = self.data[name].axi_master_idx
 518                 else:
 519                     fn = self.data[name].axi_slave_idx
 520                 (rdef, offs) = fn(start, i, idxtype)
 521                 #print ("ifc", name, rdef, offs)
 522                 ret.append(rdef)
 523                 start += offs
 524         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 525         decls = '\n'.join(list(filter(None, ret)))
 526         return template.format(decls)
 527
 528     def axi_slave_idx(self, *args):
 529         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 530                                  '', *args)
 531
 532     def axi_fastslave_idx(self, *args):
 533         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 534                                  'fast', *args)
 535
 536     def axi_master_idx(self, *args):
 537         return self._axi_num_idx(2, axi_master_declarations, 'master',
 538                                  'master', *args)
 539
 540     def axi_fastslave_idx(self, *args):
 541         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 542                                  'fast', *args)
 543
 544     def axi_addr_map(self, *args):
 545         ret = []
 546         for (name, count) in self.ifacecount:
 547             for i in range(count):
 548                 if self.is_on_fastbus(name, i):
 549                     continue
 550                 ret.append(self.data[name].axi_addr_map(i))
 551         return '\n'.join(li(list(filter(None, ret)), 8))
 552
 553     def mkfast_peripheral(self, *args):
 554         ret = []
 555         for (name, count) in self.ifacecount:
 556             for i in range(count):
 557                 if self.is_on_fastbus(name, i):
 558                     continue
 559                 #print "mkfast", name, count
 560                 x = self.data[name].mkfast_peripheral()
 561                 print name, count, x
 562                 suffix = self.data[name].mksuffix(name, i)
 563                 ret.append(x.format(suffix))
 564         return '\n'.join(li(list(filter(None, ret)), 8))
 565
 566     def mkslow_peripheral(self, *args):
 567         ret = []
 568         for (name, count) in self.ifacecount:
 569             for i in range(count):
 570                 if self.is_on_fastbus(name, i):
 571                     continue
 572                 #print "mkslow", name, count
 573                 x = self.data[name].mkslow_peripheral()
 574                 print name, count, x
 575                 suffix = self.data[name].mksuffix(name, i)
 576                 ret.append(x.format(suffix))
 577         return '\n'.join(li(list(filter(None, ret)), 8))
 578
 579     def mk_fast_connection(self, *args):
 580         ret = []
 581         for (name, count) in self.ifacecount:
 582             for i in range(count):
 583                 if self.is_on_fastbus(name, i):
 584                     continue
 585                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 586                 if name == 'gpioa':
 587                     print "txt", txt
 588                     print self.data[name].mk_connection
 589                 ret.append(txt)
 590         return '\n'.join(li(list(filter(None, ret)), 12))
 591
 592     def mk_connection(self, *args):
 593         ret = []
 594         for (name, count) in self.ifacecount:
 595             for i in range(count):
 596                 if self.is_on_fastbus(name, i):
 597                     continue
 598                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 599                 if name == 'gpioa':
 600                     print "txt", txt
 601                     print self.data[name].mk_connection
 602                 ret.append(txt)
 603         return '\n'.join(li(list(filter(None, ret)), 8))
 604
 605     def mk_cellconn(self):
 606         ret = []
 607         cellcount = 0
 608         for (name, count) in self.ifacecount:
 609             for i in range(count):
 610                 if self.is_on_fastbus(name, i):
 611                     continue
 612                 res = self.data[name].mk_cellconn(cellcount, name, i)
 613                 if not res:
 614                     continue
 615                 (txt, cellcount) = res
 616                 ret.append(txt)
 617         ret = li('\n'.join(list(filter(None, ret))), 4)
 618         return li(pinmux_cellrule.format(ret), 4)
 619
 620     def mk_pincon(self):
 621         ret = []
 622         for (name, count) in self.ifacecount:
 623             for i in range(count):
 624                 if self.is_on_fastbus(name, i):
 625                     continue
 626                 txt = self.data[name].mk_pincon(name, i)
 627                 ret.append(txt)
 628         return '\n'.join(li(list(filter(None, ret)), 4))
 629
 630     def mk_dma_irq(self):
 631         ret = []
 632         sync = []
 633         rules = []
 634         cnct = []
 635
 636         self.dma_count = 0
 637
 638         for (name, count) in self.ifacecount:
 639             ifacerules = []
 640             for i in range(count):
 641                 if not self.is_on_fastbus(name, i):
 642                     continue
 643                 txt = self.data[name].mk_dma_sync(name, i)
 644                 if txt:
 645                     self.dma_count += 1
 646                 sync.append(txt)
 647                 txt = self.data[name].mk_dma_rule(name, i)
 648                 ifacerules.append(txt)
 649                 txt = self.data[name].mk_dma_connect(name, i)
 650                 cnct.append(txt)
 651             ifacerules = list(filter(None, ifacerules))
 652             if ifacerules:
 653                 txt = "rule synchronize_%s_interrupts;" % name
 654                 rules.append(txt)
 655                 rules += ifacerules
 656                 rules.append("endrule")
 657
 658         cnct = list(filter(None, cnct))
 659         ct = self.dma_count
 660         _cnct = ["rule rl_connect_interrupt_to_DMA;",
 661                  "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 662         spc = "                      "
 663         spcsep = ",\n" + spc
 664         cnct = _cnct + [spc + spcsep.join(cnct)]
 665         cnct.append("   };")
 666         cnct.append("   dma.interrupt_from_peripherals(\n" +
 667                     "       lv_interrupt_to_DMA);")
 668         cnct.append("endrule;")
 669
 670         ret = list(filter(None, sync + rules + cnct))
 671         ret = li(ret, 15)
 672         return '\n'.join(ret)
 673
 674     def num_dmachannels(self):
 675         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 676
 677     def mk_ext_ifacedef(self):
 678         ret = []
 679         for (name, count) in self.ifacecount:
 680             for i in range(count):
 681                 if self.is_on_fastbus(name, i):
 682                     continue
 683                 txt = self.data[name].mk_ext_ifacedef(name, i)
 684                 ret.append(txt)
 685         return '\n'.join(li(list(filter(None, ret)), 8))
 686
 687     def mk_plic(self):
 688         ret = []
 689         irq_offs = 8  # XXX: DMA scovers 0-7?
 690         for (name, count) in self.ifacecount:
 691             for i in range(count):
 692                 if self.is_on_fastbus(name, i):
 693                     continue
 694                 res = self.data[name].mk_plic(i, irq_offs)
 695                 if not res:
 696                     continue
 697                 (txt, irq_offs) = res
 698                 ret.append(txt)
 699         self.num_slow_irqs = irq_offs
 700         return '\n'.join(li(list(filter(None, ret)), 4))
 701
 702     def mk_sloirqsdef(self):
 703         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 704
 705     def is_on_fastbus(self, name, i):
 706         #print "fastbus mode", self.fastbusmode, name, i
 707         iname = self.data[name].iname().format(i)
 708         if self.fastbusmode:
 709             return iname not in self.fastbus
 710         return iname in self.fastbus
 711
 712
 713 class PFactory(object):
 714     def getcls(self, name):
 715         from uart import uart
 716         from quart import quart
 717         from sdmmc import sdmmc
 718         from pwm import pwm
 719         from eint import eint
 720         from rs232 import rs232
 721         from twi import twi
 722         from eint import eint
 723         from jtag import jtag
 724         from spi import spi, mspi
 725         from qspi import qspi, mqspi
 726         from gpio import gpio
 727         from rgbttl import rgbttl
 728         from flexbus import flexbus
 729
 730         for k, v in {'uart': uart,
 731                      'rs232': rs232,
 732                      'twi': twi,
 733                      'quart': quart,
 734                      'mqspi': mqspi,
 735                      'mspi': mspi,
 736                      'qspi': qspi,
 737                      'spi': spi,
 738                      'pwm': pwm,
 739                      'eint': eint,
 740                      'sd': sdmmc,
 741                      'jtag': jtag,
 742                      'lcd': rgbttl,
 743                      'fb': flexbus,
 744                      'gpio': gpio
 745                      }.items():
 746             if name.startswith(k):
 747                 return v
 748         return None
 749
 750
 751 slowfactory = PFactory()
 752
 753 if __name__ == '__main__':
 754     p = uart('uart')
 755     print p.slowimport()
 756     print p.slowifdecl()
 757     i = PeripheralIface('uart')
 758     print i, i.slow
 759     i = PeripheralIface('gpioa')
 760     print i, i.slow