Factor out the dummy RoCC accelerator
[riscv-isa-sim.git] / config.h.in
1 /* config.h.in. Generated from configure.ac by autoheader. */
2
3 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
4 #undef DUMMY_ROCC_ENABLED
5
6 /* Define to 1 if you have the `dl' library (-ldl). */
7 #undef HAVE_LIBDL
8
9 /* Define to 1 if you have the `fesvr' library (-lfesvr). */
10 #undef HAVE_LIBFESVR
11
12 /* Define to 1 if you have the `pthread' library (-lpthread). */
13 #undef HAVE_LIBPTHREAD
14
15 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
16 #undef HWACHA_ENABLED
17
18 /* Define to the address where bug reports for this package should be sent. */
19 #undef PACKAGE_BUGREPORT
20
21 /* Define to the full name of this package. */
22 #undef PACKAGE_NAME
23
24 /* Define to the full name and version of this package. */
25 #undef PACKAGE_STRING
26
27 /* Define to the one symbol short name of this package. */
28 #undef PACKAGE_TARNAME
29
30 /* Define to the home page for this package. */
31 #undef PACKAGE_URL
32
33 /* Define to the version of this package. */
34 #undef PACKAGE_VERSION
35
36 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
37 #undef RISCV_ENABLED
38
39 /* Define if 64-bit mode is supported */
40 #undef RISCV_ENABLE_64BIT
41
42 /* Enable commit log generation */
43 #undef RISCV_ENABLE_COMMITLOG
44
45 /* Define if floating-point instructions are supported */
46 #undef RISCV_ENABLE_FPU
47
48 /* Enable PC histogram generation */
49 #undef RISCV_ENABLE_HISTOGRAM
50
51 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
52 #undef SOFTFLOAT_ENABLED
53
54 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
55 #undef SPIKE_ENABLED
56
57 /* Define to 1 if you have the ANSI C header files. */
58 #undef STDC_HEADERS