riscv/debug_defines.h

   1 #define DTM_IDCODE                          0x01
   2 /*
   3 * Identifies the release version of this part.
   4  */
   5 #define DTM_IDCODE_VERSION_OFFSET           28
   6 #define DTM_IDCODE_VERSION_LENGTH           4
   7 #define DTM_IDCODE_VERSION                  (0xfU << DTM_IDCODE_VERSION_OFFSET)
   8 /*
   9 * Identifies the designer's part number of this part.
  10  */
  11 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
  12 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
  13 #define DTM_IDCODE_PARTNUMBER               (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
  14 /*
  15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
  16 * bits 6:0 of the designer/manufacturer's Identification Code as
  17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
  18 * count of the number of continuation characters (0x7f) in that same
  19 * Identification Code.
  20  */
  21 #define DTM_IDCODE_MANUFID_OFFSET           1
  22 #define DTM_IDCODE_MANUFID_LENGTH           11
  23 #define DTM_IDCODE_MANUFID                  (0x7ffU << DTM_IDCODE_MANUFID_OFFSET)
  24 #define DTM_IDCODE_1_OFFSET                 0
  25 #define DTM_IDCODE_1_LENGTH                 1
  26 #define DTM_IDCODE_1                        (0x1U << DTM_IDCODE_1_OFFSET)
  27 #define DTM_DTMCS                           0x10
  28 /*
  29 * Writing 1 to this bit does a hard reset of the DTM,
  30 * causing the DTM to forget about any outstanding DMI transactions.
  31 * In general this should only be used when the Debugger has
  32 * reason to expect that the outstanding DMI transaction will never
  33 * complete (e.g. a reset condition caused an inflight DMI transaction to
  34 * be cancelled).
  35  */
  36 #define DTM_DTMCS_DMIHARDRESET_OFFSET       17
  37 #define DTM_DTMCS_DMIHARDRESET_LENGTH       1
  38 #define DTM_DTMCS_DMIHARDRESET              (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
  39 /*
  40 * Writing 1 to this bit clears the sticky error state
  41 * and allows the DTM to retry or complete the previous
  42 * transaction.
  43  */
  44 #define DTM_DTMCS_DMIRESET_OFFSET           16
  45 #define DTM_DTMCS_DMIRESET_LENGTH           1
  46 #define DTM_DTMCS_DMIRESET                  (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
  47 /*
  48 * This is a hint to the debugger of the minimum number of
  49 * cycles a debugger should spend in
  50 * Run-Test/Idle after every DMI scan to avoid a `busy'
  51 * return code (\Fdmistat of 3). A debugger must still
  52 * check \Fdmistat when necessary.
  53 *
  54 * 0: It is not necessary to enter Run-Test/Idle at all.
  55 *
  56 * 1: Enter Run-Test/Idle and leave it immediately.
  57 *
  58 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
  59 *
  60 * And so on.
  61  */
  62 #define DTM_DTMCS_IDLE_OFFSET               12
  63 #define DTM_DTMCS_IDLE_LENGTH               3
  64 #define DTM_DTMCS_IDLE                      (0x7U << DTM_DTMCS_IDLE_OFFSET)
  65 /*
  66 * 0: No error.
  67 *
  68 * 1: Reserved. Interpret the same as 2.
  69 *
  70 * 2: An operation failed (resulted in \Fop of 2).
  71 *
  72 * 3: An operation was attempted while a DMI access was still in
  73 * progress (resulted in \Fop of 3).
  74  */
  75 #define DTM_DTMCS_DMISTAT_OFFSET            10
  76 #define DTM_DTMCS_DMISTAT_LENGTH            2
  77 #define DTM_DTMCS_DMISTAT                   (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
  78 /*
  79 * The size of \Faddress in \Rdmi.
  80  */
  81 #define DTM_DTMCS_ABITS_OFFSET              4
  82 #define DTM_DTMCS_ABITS_LENGTH              6
  83 #define DTM_DTMCS_ABITS                     (0x3fU << DTM_DTMCS_ABITS_OFFSET)
  84 /*
  85 * 0: Version described in spec version 0.11.
  86 *
  87 * 1: Version described in spec version 0.13 (and later?), which
  88 * reduces the DMI data width to 32 bits.
  89 *
  90 * 15: Version not described in any available version of this spec.
  91  */
  92 #define DTM_DTMCS_VERSION_OFFSET            0
  93 #define DTM_DTMCS_VERSION_LENGTH            4
  94 #define DTM_DTMCS_VERSION                   (0xfU << DTM_DTMCS_VERSION_OFFSET)
  95 #define DTM_DMI                             0x11
  96 /*
  97 * Address used for DMI access. In Update-DR this value is used
  98 * to access the DM over the DMI.
  99  */
 100 #define DTM_DMI_ADDRESS_OFFSET              34
 101 #define DTM_DMI_ADDRESS_LENGTH              abits
 102 #define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
 103 /*
 104 * The data to send to the DM over the DMI during Update-DR, and
 105 * the data returned from the DM as a result of the previous operation.
 106  */
 107 #define DTM_DMI_DATA_OFFSET                 2
 108 #define DTM_DMI_DATA_LENGTH                 32
 109 #define DTM_DMI_DATA                        (0xffffffffULL << DTM_DMI_DATA_OFFSET)
 110 /*
 111 * When the debugger writes this field, it has the following meaning:
 112 *
 113 * 0: Ignore \Fdata and \Faddress. (nop)
 114 *
 115 * Don't send anything over the DMI during Update-DR.
 116 * This operation should never result in a busy or error response.
 117 * The address and data reported in the following Capture-DR
 118 * are undefined.
 119 *
 120 * 1: Read from \Faddress. (read)
 121 *
 122 * 2: Write \Fdata to \Faddress. (write)
 123 *
 124 * 3: Reserved.
 125 *
 126 * When the debugger reads this field, it means the following:
 127 *
 128 * 0: The previous operation completed successfully.
 129 *
 130 * 1: Reserved.
 131 *
 132 * 2: A previous operation failed.  The data scanned into \Rdmi in
 133 * this access will be ignored.  This status is sticky and can be
 134 * cleared by writing \Fdmireset in \Rdtmcs.
 135 *
 136 * This indicates that the DM itself responded with an error.
 137 * Note: there are no specified cases in which the DM would
 138 * respond with an error, and DMI is not required to support
 139 * returning errors.
 140 *
 141 * 3: An operation was attempted while a DMI request is still in
 142 * progress. The data scanned into \Rdmi in this access will be
 143 * ignored. This status is sticky and can be cleared by writing
 144 * \Fdmireset in \Rdtmcs. If a debugger sees this status, it
 145 * needs to give the target more TCK edges between Update-DR and
 146 * Capture-DR. The simplest way to do that is to add extra transitions
 147 * in Run-Test/Idle.
 148 *
 149 * (The DTM, DM, and/or component may be in different clock domains,
 150 * so synchronization may be required. Some relatively fixed number of
 151 * TCK ticks may be needed for the request to reach the DM, complete,
 152 * and for the response to be synchronized back into the TCK domain.)
 153  */
 154 #define DTM_DMI_OP_OFFSET                   0
 155 #define DTM_DMI_OP_LENGTH                   2
 156 #define DTM_DMI_OP                          (0x3ULL << DTM_DMI_OP_OFFSET)
 157 #define CSR_DCSR                            0x7b0
 158 /*
 159 * 0: There is no external debug support.
 160 *
 161 * 4: External debug support exists as it is described in this document.
 162 *
 163 * 15: There is external debug support, but it does not conform to any
 164 * available version of this spec.
 165  */
 166 #define CSR_DCSR_XDEBUGVER_OFFSET           28
 167 #define CSR_DCSR_XDEBUGVER_LENGTH           4
 168 #define CSR_DCSR_XDEBUGVER                  (0xfU << CSR_DCSR_XDEBUGVER_OFFSET)
 169 /*
 170 * When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode.
 171  */
 172 #define CSR_DCSR_EBREAKM_OFFSET             15
 173 #define CSR_DCSR_EBREAKM_LENGTH             1
 174 #define CSR_DCSR_EBREAKM                    (0x1U << CSR_DCSR_EBREAKM_OFFSET)
 175 /*
 176 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode.
 177  */
 178 #define CSR_DCSR_EBREAKS_OFFSET             13
 179 #define CSR_DCSR_EBREAKS_LENGTH             1
 180 #define CSR_DCSR_EBREAKS                    (0x1U << CSR_DCSR_EBREAKS_OFFSET)
 181 /*
 182 * When 1, {\tt ebreak} instructions in User/Application Mode enter
 183 * Debug Mode.
 184  */
 185 #define CSR_DCSR_EBREAKU_OFFSET             12
 186 #define CSR_DCSR_EBREAKU_LENGTH             1
 187 #define CSR_DCSR_EBREAKU                    (0x1U << CSR_DCSR_EBREAKU_OFFSET)
 188 /*
 189 * 0: Interrupts are disabled during single stepping.
 190 *
 191 * 1: Interrupts are enabled during single stepping.
 192 *
 193 * Implementations may hard wire this bit to 0.
 194 * The debugger must read back the value it
 195 * writes to check whether the feature is supported. If not
 196 * supported, interrupt behavior can be emulated by the debugger.
 197  */
 198 #define CSR_DCSR_STEPIE_OFFSET              11
 199 #define CSR_DCSR_STEPIE_LENGTH              1
 200 #define CSR_DCSR_STEPIE                     (0x1U << CSR_DCSR_STEPIE_OFFSET)
 201 /*
 202 * 0: Increment counters as usual.
 203 *
 204 * 1: Don't increment any counters while in Debug Mode or on {\tt
 205 * ebreak} instructions that cause entry into Debug Mode.  These
 206 * counters include the {\tt cycle} and {\tt instret} CSRs. This is
 207 * preferred for most debugging scenarios.
 208 *
 209 * An implementation may choose not to support writing to this bit.
 210 * The debugger must read back the value it writes to check whether
 211 * the feature is supported.
 212  */
 213 #define CSR_DCSR_STOPCOUNT_OFFSET           10
 214 #define CSR_DCSR_STOPCOUNT_LENGTH           1
 215 #define CSR_DCSR_STOPCOUNT                  (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
 216 /*
 217 * 0: Increment timers as usual.
 218 *
 219 * 1: Don't increment any hart-local timers while in Debug Mode.
 220 *
 221 * An implementation may choose not to support writing to this bit.
 222 * The debugger must read back the value it writes to check whether
 223 * the feature is supported.
 224  */
 225 #define CSR_DCSR_STOPTIME_OFFSET            9
 226 #define CSR_DCSR_STOPTIME_LENGTH            1
 227 #define CSR_DCSR_STOPTIME                   (0x1U << CSR_DCSR_STOPTIME_OFFSET)
 228 /*
 229 * Explains why Debug Mode was entered.
 230 *
 231 * When there are multiple reasons to enter Debug Mode in a single
 232 * cycle, hardware should set \Fcause to the cause with the highest
 233 * priority.
 234 *
 235 * 1: An {\tt ebreak} instruction was executed. (priority 3)
 236 *
 237 * 2: The Trigger Module caused a breakpoint exception. (priority 4)
 238 *
 239 * 3: The debugger requested entry to Debug Mode. (priority 2)
 240 *
 241 * 4: The hart single stepped because \Fstep was set. (priority 1)
 242 *
 243 * Other values are reserved for future use.
 244  */
 245 #define CSR_DCSR_CAUSE_OFFSET               6
 246 #define CSR_DCSR_CAUSE_LENGTH               3
 247 #define CSR_DCSR_CAUSE                      (0x7U << CSR_DCSR_CAUSE_OFFSET)
 248 /*
 249 * When 1, \Fmprv in \Rmstatus takes effect during debug mode.
 250 * When 0, it is ignored during debug mode.
 251 * Implementing this bit is optional.
 252 * If not implemented it should be tied to 0.
 253  */
 254 #define CSR_DCSR_MPRVEN_OFFSET              4
 255 #define CSR_DCSR_MPRVEN_LENGTH              1
 256 #define CSR_DCSR_MPRVEN                     (0x1U << CSR_DCSR_MPRVEN_OFFSET)
 257 /*
 258 * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
 259 *
 260 * Since an NMI can indicate a hardware error condition,
 261 * reliable debugging may no longer be possible once this bit becomes set.
 262 * This is implementation-dependent.
 263  */
 264 #define CSR_DCSR_NMIP_OFFSET                3
 265 #define CSR_DCSR_NMIP_LENGTH                1
 266 #define CSR_DCSR_NMIP                       (0x1U << CSR_DCSR_NMIP_OFFSET)
 267 /*
 268 * When set and not in Debug Mode, the hart will only execute a single
 269 * instruction and then enter Debug Mode.
 270 * If the instruction does not complete due to an exception,
 271 * the hart will immediately enter Debug Mode before executing
 272 * the trap handler, with appropriate exception registers set.
 273  */
 274 #define CSR_DCSR_STEP_OFFSET                2
 275 #define CSR_DCSR_STEP_LENGTH                1
 276 #define CSR_DCSR_STEP                       (0x1U << CSR_DCSR_STEP_OFFSET)
 277 /*
 278 * Contains the privilege level the hart was operating in when Debug
 279 * Mode was entered. The encoding is described in Table
 280 * \ref{tab:privlevel}.  A debugger can change this value to change
 281 * the hart's privilege level when exiting Debug Mode.
 282 *
 283 * Not all privilege levels are supported on all harts. If the
 284 * encoding written is not supported or the debugger is not allowed to
 285 * change to it, the hart may change to any supported privilege level.
 286  */
 287 #define CSR_DCSR_PRV_OFFSET                 0
 288 #define CSR_DCSR_PRV_LENGTH                 2
 289 #define CSR_DCSR_PRV                        (0x3U << CSR_DCSR_PRV_OFFSET)
 290 #define CSR_DPC                             0x7b1
 291 #define CSR_DPC_DPC_OFFSET                  0
 292 #define CSR_DPC_DPC_LENGTH                  MXLEN
 293 #define CSR_DPC_DPC                         (((1L<<MXLEN)-1) << CSR_DPC_DPC_OFFSET)
 294 #define CSR_DSCRATCH0                       0x7b2
 295 #define CSR_DSCRATCH1                       0x7b3
 296 #define CSR_TSELECT                         0x7a0
 297 #define CSR_TSELECT_INDEX_OFFSET            0
 298 #define CSR_TSELECT_INDEX_LENGTH            MXLEN
 299 #define CSR_TSELECT_INDEX                   (((1L<<MXLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
 300 #define CSR_TDATA1                          0x7a1
 301 /*
 302 * 0: There is no trigger at this \Rtselect.
 303 *
 304 * 1: The trigger is a legacy SiFive address match trigger. These
 305 * should not be implemented and aren't further documented here.
 306 *
 307 * 2: The trigger is an address/data match trigger. The remaining bits
 308 * in this register act as described in \Rmcontrol.
 309 *
 310 * 3: The trigger is an instruction count trigger. The remaining bits
 311 * in this register act as described in \Ricount.
 312 *
 313 * 4: The trigger is an interrupt trigger. The remaining bits
 314 * in this register act as described in \Ritrigger.
 315 *
 316 * 5: The trigger is an exception trigger. The remaining bits
 317 * in this register act as described in \Retrigger.
 318 *
 319 * 15: This trigger exists (so enumeration shouldn't terminate), but
 320 * is not currently available.
 321 *
 322 * Other values are reserved for future use.
 323 *
 324 * When this field is written to an unsupported value, it takes on its
 325 * reset value instead. The reset value is any one of the types
 326 * supported by the trigger selected by \Rtselect.
 327  */
 328 #define CSR_TDATA1_TYPE_OFFSET              (MXLEN-4)
 329 #define CSR_TDATA1_TYPE_LENGTH              4
 330 #define CSR_TDATA1_TYPE                     (0xfULL << CSR_TDATA1_TYPE_OFFSET)
 331 /*
 332 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the
 333 * selected \Rtselect.
 334 *
 335 * 1: Only Debug Mode can write the {\tt tdata} registers at the
 336 * selected \Rtselect.  Writes from other modes are ignored.
 337 *
 338 * This bit is only writable from Debug Mode.
 339  */
 340 #define CSR_TDATA1_DMODE_OFFSET             (MXLEN-5)
 341 #define CSR_TDATA1_DMODE_LENGTH             1
 342 #define CSR_TDATA1_DMODE                    (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
 343 /*
 344 * Trigger-specific data.
 345  */
 346 #define CSR_TDATA1_DATA_OFFSET              0
 347 #define CSR_TDATA1_DATA_LENGTH              (MXLEN - 5)
 348 #define CSR_TDATA1_DATA                     (((1L<<MXLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
 349 #define CSR_TDATA2                          0x7a2
 350 #define CSR_TDATA2_DATA_OFFSET              0
 351 #define CSR_TDATA2_DATA_LENGTH              MXLEN
 352 #define CSR_TDATA2_DATA                     (((1L<<MXLEN)-1) << CSR_TDATA2_DATA_OFFSET)
 353 #define CSR_TDATA3                          0x7a3
 354 #define CSR_TDATA3_DATA_OFFSET              0
 355 #define CSR_TDATA3_DATA_LENGTH              MXLEN
 356 #define CSR_TDATA3_DATA                     (((1L<<MXLEN)-1) << CSR_TDATA3_DATA_OFFSET)
 357 #define CSR_TINFO                           0x7a4
 358 /*
 359 * One bit for each possible \Ftype enumerated in \Rtdataone. Bit N
 360 * corresponds to type N. If the bit is set, then that type is
 361 * supported by the currently selected trigger.
 362 *
 363 * If the currently selected trigger doesn't exist, this field
 364 * contains 1.
 365 *
 366 * If \Ftype is not writable, this register may be unimplemented, in
 367 * which case reading it causes an illegal instruction exception. In
 368 * this case the debugger can read the only supported type from
 369 * \Rtdataone.
 370  */
 371 #define CSR_TINFO_INFO_OFFSET               0
 372 #define CSR_TINFO_INFO_LENGTH               16
 373 #define CSR_TINFO_INFO                      (0xffffULL << CSR_TINFO_INFO_OFFSET)
 374 #define CSR_MCONTROL                        0x7a1
 375 #define CSR_MCONTROL_TYPE_OFFSET            (MXLEN-4)
 376 #define CSR_MCONTROL_TYPE_LENGTH            4
 377 #define CSR_MCONTROL_TYPE                   (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
 378 #define CSR_MCONTROL_DMODE_OFFSET           (MXLEN-5)
 379 #define CSR_MCONTROL_DMODE_LENGTH           1
 380 #define CSR_MCONTROL_DMODE                  (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
 381 /*
 382 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
 383 * supported by the hardware when \Fmatch is 1. The value is the
 384 * logarithm base 2 of the
 385 * number of bytes in that range.  A value of 0 indicates that only
 386 * exact value matches are supported (one byte range). A value of 63
 387 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
 388 * size.
 389  */
 390 #define CSR_MCONTROL_MASKMAX_OFFSET         (MXLEN-11)
 391 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 392 #define CSR_MCONTROL_MASKMAX                (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
 393 /*
 394 * If this optional bit is implemented, the hardware sets it when this
 395 * trigger matches. The trigger's user can set or clear it at any
 396 * time. The trigger's user can use this bit to determine which
 397 * trigger(s) matched.  If the bit is not implemented, it is always 0
 398 * and writing it has no effect.
 399  */
 400 #define CSR_MCONTROL_HIT_OFFSET             20
 401 #define CSR_MCONTROL_HIT_LENGTH             1
 402 #define CSR_MCONTROL_HIT                    (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
 403 /*
 404 * 0: Perform a match on the virtual address.
 405 *
 406 * 1: Perform a match on the data value loaded/stored, or the
 407 * instruction executed.
 408  */
 409 #define CSR_MCONTROL_SELECT_OFFSET          19
 410 #define CSR_MCONTROL_SELECT_LENGTH          1
 411 #define CSR_MCONTROL_SELECT                 (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
 412 /*
 413 * 0: The action for this trigger will be taken just before the
 414 * instruction that triggered it is executed, but after all preceding
 415 * instructions are are committed.
 416 *
 417 * 1: The action for this trigger will be taken after the instruction
 418 * that triggered it is executed. It should be taken before the next
 419 * instruction is executed, but it is better to implement triggers and
 420 * not implement that suggestion than to not implement them at all.
 421 *
 422 * Most hardware will only implement one timing or the other, possibly
 423 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
 424 * primarily exists for the hardware to communicate to the debugger
 425 * what will happen. Hardware may implement the bit fully writable, in
 426 * which case the debugger has a little more control.
 427 *
 428 * Data load triggers with \Ftiming of 0 will result in the same load
 429 * happening again when the debugger lets the hart run. For data load
 430 * triggers, debuggers must first attempt to set the breakpoint with
 431 * \Ftiming of 1.
 432 *
 433 * A chain of triggers that don't all have the same \Ftiming value
 434 * will never fire (unless consecutive instructions match the
 435 * appropriate triggers).
 436  */
 437 #define CSR_MCONTROL_TIMING_OFFSET          18
 438 #define CSR_MCONTROL_TIMING_LENGTH          1
 439 #define CSR_MCONTROL_TIMING                 (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
 440 /*
 441 * The action to take when the trigger fires. The values are explained
 442 * in Table~\ref{tab:action}.
 443  */
 444 #define CSR_MCONTROL_ACTION_OFFSET          12
 445 #define CSR_MCONTROL_ACTION_LENGTH          6
 446 #define CSR_MCONTROL_ACTION                 (0x3fULL << CSR_MCONTROL_ACTION_OFFSET)
 447 /*
 448 * 0: When this trigger matches, the configured action is taken.
 449 *
 450 * 1: While this trigger does not match, it prevents the trigger with
 451 * the next index from matching.
 452 *
 453 * Because \Fchain affects the next trigger, hardware must zero it in
 454 * writes to \Rmcontrol that set \Fdmode to 0 if the next trigger has
 455 * \Fdmode of 1.
 456 * In addition hardware should ignore writes to \Rmcontrol that set
 457 * \Fdmode to 1 if the previous trigger has both \Fdmode of 0 and
 458 * \Fchain of 1. Debuggers must avoid the latter case by checking
 459 * \Fchain on the previous trigger if they're writing \Rmcontrol.
 460 *
 461 * Implementations that wish to limit the maximum length of a trigger
 462 * chain (eg. to meet timing requirements) may do so by zeroing
 463 * \Fchain in writes to \Rmcontrol that would make the chain too long.
 464  */
 465 #define CSR_MCONTROL_CHAIN_OFFSET           11
 466 #define CSR_MCONTROL_CHAIN_LENGTH           1
 467 #define CSR_MCONTROL_CHAIN                  (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
 468 /*
 469 * 0: Matches when the value equals \Rtdatatwo.
 470 *
 471 * 1: Matches when the top M bits of the value match the top M bits of
 472 * \Rtdatatwo. M is MXLEN-1 minus the index of the least-significant
 473 * bit containing 0 in \Rtdatatwo.
 474 *
 475 * 2: Matches when the value is greater than (unsigned) or equal to
 476 * \Rtdatatwo.
 477 *
 478 * 3: Matches when the value is less than (unsigned) \Rtdatatwo.
 479 *
 480 * 4: Matches when the lower half of the value equals the lower half
 481 * of \Rtdatatwo after the lower half of the value is ANDed with the
 482 * upper half of \Rtdatatwo.
 483 *
 484 * 5: Matches when the upper half of the value equals the lower half
 485 * of \Rtdatatwo after the upper half of the value is ANDed with the
 486 * upper half of \Rtdatatwo.
 487 *
 488 * Other values are reserved for future use.
 489  */
 490 #define CSR_MCONTROL_MATCH_OFFSET           7
 491 #define CSR_MCONTROL_MATCH_LENGTH           4
 492 #define CSR_MCONTROL_MATCH                  (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
 493 /*
 494 * When set, enable this trigger in M mode.
 495  */
 496 #define CSR_MCONTROL_M_OFFSET               6
 497 #define CSR_MCONTROL_M_LENGTH               1
 498 #define CSR_MCONTROL_M                      (0x1ULL << CSR_MCONTROL_M_OFFSET)
 499 /*
 500 * When set, enable this trigger in S mode.
 501  */
 502 #define CSR_MCONTROL_S_OFFSET               4
 503 #define CSR_MCONTROL_S_LENGTH               1
 504 #define CSR_MCONTROL_S                      (0x1ULL << CSR_MCONTROL_S_OFFSET)
 505 /*
 506 * When set, enable this trigger in U mode.
 507  */
 508 #define CSR_MCONTROL_U_OFFSET               3
 509 #define CSR_MCONTROL_U_LENGTH               1
 510 #define CSR_MCONTROL_U                      (0x1ULL << CSR_MCONTROL_U_OFFSET)
 511 /*
 512 * When set, the trigger fires on the virtual address or opcode of an
 513 * instruction that is executed.
 514  */
 515 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 516 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 517 #define CSR_MCONTROL_EXECUTE                (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
 518 /*
 519 * When set, the trigger fires on the virtual address or data of a store.
 520  */
 521 #define CSR_MCONTROL_STORE_OFFSET           1
 522 #define CSR_MCONTROL_STORE_LENGTH           1
 523 #define CSR_MCONTROL_STORE                  (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
 524 /*
 525 * When set, the trigger fires on the virtual address or data of a load.
 526  */
 527 #define CSR_MCONTROL_LOAD_OFFSET            0
 528 #define CSR_MCONTROL_LOAD_LENGTH            1
 529 #define CSR_MCONTROL_LOAD                   (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
 530 #define CSR_ICOUNT                          0x7a1
 531 #define CSR_ICOUNT_TYPE_OFFSET              (MXLEN-4)
 532 #define CSR_ICOUNT_TYPE_LENGTH              4
 533 #define CSR_ICOUNT_TYPE                     (0xfULL << CSR_ICOUNT_TYPE_OFFSET)
 534 #define CSR_ICOUNT_DMODE_OFFSET             (MXLEN-5)
 535 #define CSR_ICOUNT_DMODE_LENGTH             1
 536 #define CSR_ICOUNT_DMODE                    (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
 537 /*
 538 * If this optional bit is implemented, the hardware sets it when this
 539 * trigger matches. The trigger's user can set or clear it at any
 540 * time. The trigger's user can use this bit to determine which
 541 * trigger(s) matched.  If the bit is not implemented, it is always 0
 542 * and writing it has no effect.
 543  */
 544 #define CSR_ICOUNT_HIT_OFFSET               24
 545 #define CSR_ICOUNT_HIT_LENGTH               1
 546 #define CSR_ICOUNT_HIT                      (0x1ULL << CSR_ICOUNT_HIT_OFFSET)
 547 /*
 548 * When count is decremented to 0, the trigger fires. Instead of
 549 * changing \Fcount from 1 to 0, it is also acceptable for hardware to
 550 * clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired
 551 * to 1 if this register just exists for single step.
 552  */
 553 #define CSR_ICOUNT_COUNT_OFFSET             10
 554 #define CSR_ICOUNT_COUNT_LENGTH             14
 555 #define CSR_ICOUNT_COUNT                    (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET)
 556 /*
 557 * When set, every instruction completed or exception taken in M mode decrements \Fcount
 558 * by 1.
 559  */
 560 #define CSR_ICOUNT_M_OFFSET                 9
 561 #define CSR_ICOUNT_M_LENGTH                 1
 562 #define CSR_ICOUNT_M                        (0x1ULL << CSR_ICOUNT_M_OFFSET)
 563 /*
 564 * When set, every instruction completed or exception taken in S mode decrements \Fcount
 565 * by 1.
 566  */
 567 #define CSR_ICOUNT_S_OFFSET                 7
 568 #define CSR_ICOUNT_S_LENGTH                 1
 569 #define CSR_ICOUNT_S                        (0x1ULL << CSR_ICOUNT_S_OFFSET)
 570 /*
 571 * When set, every instruction completed or exception taken in U mode decrements \Fcount
 572 * by 1.
 573  */
 574 #define CSR_ICOUNT_U_OFFSET                 6
 575 #define CSR_ICOUNT_U_LENGTH                 1
 576 #define CSR_ICOUNT_U                        (0x1ULL << CSR_ICOUNT_U_OFFSET)
 577 /*
 578 * The action to take when the trigger fires. The values are explained
 579 * in Table~\ref{tab:action}.
 580  */
 581 #define CSR_ICOUNT_ACTION_OFFSET            0
 582 #define CSR_ICOUNT_ACTION_LENGTH            6
 583 #define CSR_ICOUNT_ACTION                   (0x3fULL << CSR_ICOUNT_ACTION_OFFSET)
 584 #define CSR_ITRIGGER                        0x7a1
 585 #define CSR_ITRIGGER_TYPE_OFFSET            (MXLEN-4)
 586 #define CSR_ITRIGGER_TYPE_LENGTH            4
 587 #define CSR_ITRIGGER_TYPE                   (0xfULL << CSR_ITRIGGER_TYPE_OFFSET)
 588 #define CSR_ITRIGGER_DMODE_OFFSET           (MXLEN-5)
 589 #define CSR_ITRIGGER_DMODE_LENGTH           1
 590 #define CSR_ITRIGGER_DMODE                  (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET)
 591 /*
 592 * If this optional bit is implemented, the hardware sets it when this
 593 * trigger matches. The trigger's user can set or clear it at any
 594 * time. The trigger's user can use this bit to determine which
 595 * trigger(s) matched.  If the bit is not implemented, it is always 0
 596 * and writing it has no effect.
 597  */
 598 #define CSR_ITRIGGER_HIT_OFFSET             (MXLEN-6)
 599 #define CSR_ITRIGGER_HIT_LENGTH             1
 600 #define CSR_ITRIGGER_HIT                    (0x1ULL << CSR_ITRIGGER_HIT_OFFSET)
 601 /*
 602 * When set, enable this trigger for interrupts that are taken from M
 603 * mode.
 604  */
 605 #define CSR_ITRIGGER_M_OFFSET               9
 606 #define CSR_ITRIGGER_M_LENGTH               1
 607 #define CSR_ITRIGGER_M                      (0x1ULL << CSR_ITRIGGER_M_OFFSET)
 608 /*
 609 * When set, enable this trigger for interrupts that are taken from S
 610 * mode.
 611  */
 612 #define CSR_ITRIGGER_S_OFFSET               7
 613 #define CSR_ITRIGGER_S_LENGTH               1
 614 #define CSR_ITRIGGER_S                      (0x1ULL << CSR_ITRIGGER_S_OFFSET)
 615 /*
 616 * When set, enable this trigger for interrupts that are taken from U
 617 * mode.
 618  */
 619 #define CSR_ITRIGGER_U_OFFSET               6
 620 #define CSR_ITRIGGER_U_LENGTH               1
 621 #define CSR_ITRIGGER_U                      (0x1ULL << CSR_ITRIGGER_U_OFFSET)
 622 /*
 623 * The action to take when the trigger fires. The values are explained
 624 * in Table~\ref{tab:action}.
 625  */
 626 #define CSR_ITRIGGER_ACTION_OFFSET          0
 627 #define CSR_ITRIGGER_ACTION_LENGTH          6
 628 #define CSR_ITRIGGER_ACTION                 (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET)
 629 #define CSR_ETRIGGER                        0x7a1
 630 #define CSR_ETRIGGER_TYPE_OFFSET            (MXLEN-4)
 631 #define CSR_ETRIGGER_TYPE_LENGTH            4
 632 #define CSR_ETRIGGER_TYPE                   (0xfULL << CSR_ETRIGGER_TYPE_OFFSET)
 633 #define CSR_ETRIGGER_DMODE_OFFSET           (MXLEN-5)
 634 #define CSR_ETRIGGER_DMODE_LENGTH           1
 635 #define CSR_ETRIGGER_DMODE                  (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET)
 636 /*
 637 * If this optional bit is implemented, the hardware sets it when this
 638 * trigger matches. The trigger's user can set or clear it at any
 639 * time. The trigger's user can use this bit to determine which
 640 * trigger(s) matched.  If the bit is not implemented, it is always 0
 641 * and writing it has no effect.
 642  */
 643 #define CSR_ETRIGGER_HIT_OFFSET             (MXLEN-6)
 644 #define CSR_ETRIGGER_HIT_LENGTH             1
 645 #define CSR_ETRIGGER_HIT                    (0x1ULL << CSR_ETRIGGER_HIT_OFFSET)
 646 /*
 647 * When set, enable this trigger for exceptions that are taken from M
 648 * mode.
 649  */
 650 #define CSR_ETRIGGER_M_OFFSET               9
 651 #define CSR_ETRIGGER_M_LENGTH               1
 652 #define CSR_ETRIGGER_M                      (0x1ULL << CSR_ETRIGGER_M_OFFSET)
 653 /*
 654 * When set, enable this trigger for exceptions that are taken from S
 655 * mode.
 656  */
 657 #define CSR_ETRIGGER_S_OFFSET               7
 658 #define CSR_ETRIGGER_S_LENGTH               1
 659 #define CSR_ETRIGGER_S                      (0x1ULL << CSR_ETRIGGER_S_OFFSET)
 660 /*
 661 * When set, enable this trigger for exceptions that are taken from U
 662 * mode.
 663  */
 664 #define CSR_ETRIGGER_U_OFFSET               6
 665 #define CSR_ETRIGGER_U_LENGTH               1
 666 #define CSR_ETRIGGER_U                      (0x1ULL << CSR_ETRIGGER_U_OFFSET)
 667 /*
 668 * The action to take when the trigger fires. The values are explained
 669 * in Table~\ref{tab:action}.
 670  */
 671 #define CSR_ETRIGGER_ACTION_OFFSET          0
 672 #define CSR_ETRIGGER_ACTION_LENGTH          6
 673 #define CSR_ETRIGGER_ACTION                 (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET)
 674 #define DMI_DMSTATUS                        0x11
 675 /*
 676 * If 1, then there is an implicit {\tt ebreak} instruction at the
 677 * non-existent word immediately after the Program Buffer. This saves
 678 * the debugger from having to write the {\tt ebreak} itself, and
 679 * allows the Program Buffer to be one word smaller.
 680 *
 681 * This must be 1 when \Fprogbufsize is 1.
 682  */
 683 #define DMI_DMSTATUS_IMPEBREAK_OFFSET       22
 684 #define DMI_DMSTATUS_IMPEBREAK_LENGTH       1
 685 #define DMI_DMSTATUS_IMPEBREAK              (0x1U << DMI_DMSTATUS_IMPEBREAK_OFFSET)
 686 /*
 687 * This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged.
 688  */
 689 #define DMI_DMSTATUS_ALLHAVERESET_OFFSET    19
 690 #define DMI_DMSTATUS_ALLHAVERESET_LENGTH    1
 691 #define DMI_DMSTATUS_ALLHAVERESET           (0x1U << DMI_DMSTATUS_ALLHAVERESET_OFFSET)
 692 /*
 693 * This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged.
 694  */
 695 #define DMI_DMSTATUS_ANYHAVERESET_OFFSET    18
 696 #define DMI_DMSTATUS_ANYHAVERESET_LENGTH    1
 697 #define DMI_DMSTATUS_ANYHAVERESET           (0x1U << DMI_DMSTATUS_ANYHAVERESET_OFFSET)
 698 /*
 699 * This field is 1 when all currently selected harts have acknowledged
 700 * the previous resume request.
 701  */
 702 #define DMI_DMSTATUS_ALLRESUMEACK_OFFSET    17
 703 #define DMI_DMSTATUS_ALLRESUMEACK_LENGTH    1
 704 #define DMI_DMSTATUS_ALLRESUMEACK           (0x1U << DMI_DMSTATUS_ALLRESUMEACK_OFFSET)
 705 /*
 706 * This field is 1 when any currently selected hart has acknowledged
 707 * the previous resume request.
 708  */
 709 #define DMI_DMSTATUS_ANYRESUMEACK_OFFSET    16
 710 #define DMI_DMSTATUS_ANYRESUMEACK_LENGTH    1
 711 #define DMI_DMSTATUS_ANYRESUMEACK           (0x1U << DMI_DMSTATUS_ANYRESUMEACK_OFFSET)
 712 /*
 713 * This field is 1 when all currently selected harts do not exist in this system.
 714  */
 715 #define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET  15
 716 #define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH  1
 717 #define DMI_DMSTATUS_ALLNONEXISTENT         (0x1U << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET)
 718 /*
 719 * This field is 1 when any currently selected hart does not exist in this system.
 720  */
 721 #define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET  14
 722 #define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH  1
 723 #define DMI_DMSTATUS_ANYNONEXISTENT         (0x1U << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET)
 724 /*
 725 * This field is 1 when all currently selected harts are unavailable.
 726  */
 727 #define DMI_DMSTATUS_ALLUNAVAIL_OFFSET      13
 728 #define DMI_DMSTATUS_ALLUNAVAIL_LENGTH      1
 729 #define DMI_DMSTATUS_ALLUNAVAIL             (0x1U << DMI_DMSTATUS_ALLUNAVAIL_OFFSET)
 730 /*
 731 * This field is 1 when any currently selected hart is unavailable.
 732  */
 733 #define DMI_DMSTATUS_ANYUNAVAIL_OFFSET      12
 734 #define DMI_DMSTATUS_ANYUNAVAIL_LENGTH      1
 735 #define DMI_DMSTATUS_ANYUNAVAIL             (0x1U << DMI_DMSTATUS_ANYUNAVAIL_OFFSET)
 736 /*
 737 * This field is 1 when all currently selected harts are running.
 738  */
 739 #define DMI_DMSTATUS_ALLRUNNING_OFFSET      11
 740 #define DMI_DMSTATUS_ALLRUNNING_LENGTH      1
 741 #define DMI_DMSTATUS_ALLRUNNING             (0x1U << DMI_DMSTATUS_ALLRUNNING_OFFSET)
 742 /*
 743 * This field is 1 when any currently selected hart is running.
 744  */
 745 #define DMI_DMSTATUS_ANYRUNNING_OFFSET      10
 746 #define DMI_DMSTATUS_ANYRUNNING_LENGTH      1
 747 #define DMI_DMSTATUS_ANYRUNNING             (0x1U << DMI_DMSTATUS_ANYRUNNING_OFFSET)
 748 /*
 749 * This field is 1 when all currently selected harts are halted.
 750  */
 751 #define DMI_DMSTATUS_ALLHALTED_OFFSET       9
 752 #define DMI_DMSTATUS_ALLHALTED_LENGTH       1
 753 #define DMI_DMSTATUS_ALLHALTED              (0x1U << DMI_DMSTATUS_ALLHALTED_OFFSET)
 754 /*
 755 * This field is 1 when any currently selected hart is halted.
 756  */
 757 #define DMI_DMSTATUS_ANYHALTED_OFFSET       8
 758 #define DMI_DMSTATUS_ANYHALTED_LENGTH       1
 759 #define DMI_DMSTATUS_ANYHALTED              (0x1U << DMI_DMSTATUS_ANYHALTED_OFFSET)
 760 /*
 761 * 0 when authentication is required before using the DM.  1 when the
 762 * authentication check has passed. On components that don't implement
 763 * authentication, this bit must be preset as 1.
 764  */
 765 #define DMI_DMSTATUS_AUTHENTICATED_OFFSET   7
 766 #define DMI_DMSTATUS_AUTHENTICATED_LENGTH   1
 767 #define DMI_DMSTATUS_AUTHENTICATED          (0x1U << DMI_DMSTATUS_AUTHENTICATED_OFFSET)
 768 /*
 769 * 0: The authentication module is ready to process the next
 770 * read/write to \Rauthdata.
 771 *
 772 * 1: The authentication module is busy. Accessing \Rauthdata results
 773 * in unspecified behavior.
 774 *
 775 * \Fauthbusy only becomes set in immediate response to an access to
 776 * \Rauthdata.
 777  */
 778 #define DMI_DMSTATUS_AUTHBUSY_OFFSET        6
 779 #define DMI_DMSTATUS_AUTHBUSY_LENGTH        1
 780 #define DMI_DMSTATUS_AUTHBUSY               (0x1U << DMI_DMSTATUS_AUTHBUSY_OFFSET)
 781 /*
 782 * 1 if this Debug Module supports halt-on-reset functionality
 783 * controllable by the \Fsetresethaltreq and \Fclrresethaltreq bits.
 784 * 0 otherwise.
 785  */
 786 #define DMI_DMSTATUS_HASRESETHALTREQ_OFFSET 5
 787 #define DMI_DMSTATUS_HASRESETHALTREQ_LENGTH 1
 788 #define DMI_DMSTATUS_HASRESETHALTREQ        (0x1U << DMI_DMSTATUS_HASRESETHALTREQ_OFFSET)
 789 /*
 790 * 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which
 791 * is not relevant to the Device Tree.
 792 *
 793 * 1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the
 794 * Device Tree.
 795  */
 796 #define DMI_DMSTATUS_DEVTREEVALID_OFFSET    4
 797 #define DMI_DMSTATUS_DEVTREEVALID_LENGTH    1
 798 #define DMI_DMSTATUS_DEVTREEVALID           (0x1U << DMI_DMSTATUS_DEVTREEVALID_OFFSET)
 799 /*
 800 * 0: There is no Debug Module present.
 801 *
 802 * 1: There is a Debug Module and it conforms to version 0.11 of this
 803 * specification.
 804 *
 805 * 2: There is a Debug Module and it conforms to version 0.13 of this
 806 * specification.
 807 *
 808 * 15: There is a Debug Module but it does not conform to any
 809 * available version of this spec.
 810  */
 811 #define DMI_DMSTATUS_VERSION_OFFSET         0
 812 #define DMI_DMSTATUS_VERSION_LENGTH         4
 813 #define DMI_DMSTATUS_VERSION                (0xfU << DMI_DMSTATUS_VERSION_OFFSET)
 814 #define DMI_DMCONTROL                       0x10
 815 /*
 816 * Writes the halt request bit for all currently selected harts.
 817 * When set to 1, each selected hart will halt if it is not currently
 818 * halted.
 819 *
 820 * Writing 1 or 0 has no effect on a hart which is already halted, but
 821 * the bit must be cleared to 0 before the hart is resumed.
 822 *
 823 * Writes apply to the new value of \Fhartsel and \Fhasel.
 824  */
 825 #define DMI_DMCONTROL_HALTREQ_OFFSET        31
 826 #define DMI_DMCONTROL_HALTREQ_LENGTH        1
 827 #define DMI_DMCONTROL_HALTREQ               (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET)
 828 /*
 829 * Writes the resume request bit for all currently selected harts.
 830 * When set to 1, each selected hart will resume if it is currently
 831 * halted.
 832 *
 833 * The resume request bit is ignored while the halt request bit is
 834 * set.
 835 *
 836 * Writes apply to the new value of \Fhartsel and \Fhasel.
 837  */
 838 #define DMI_DMCONTROL_RESUMEREQ_OFFSET      30
 839 #define DMI_DMCONTROL_RESUMEREQ_LENGTH      1
 840 #define DMI_DMCONTROL_RESUMEREQ             (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET)
 841 /*
 842 * This optional field writes the reset bit for all the currently
 843 * selected harts.  To perform a reset the debugger writes 1, and then
 844 * writes 0 to deassert the reset signal.
 845 *
 846 * If this feature is not implemented, the bit always stays 0, so
 847 * after writing 1 the debugger can read the register back to see if
 848 * the feature is supported.
 849 *
 850 * Writes apply to the new value of \Fhartsel and \Fhasel.
 851  */
 852 #define DMI_DMCONTROL_HARTRESET_OFFSET      29
 853 #define DMI_DMCONTROL_HARTRESET_LENGTH      1
 854 #define DMI_DMCONTROL_HARTRESET             (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET)
 855 /*
 856 * Writing 1 to this bit clears the {\tt havereset} bits for
 857 * any selected harts.
 858 *
 859 * Writes apply to the new value of \Fhartsel and \Fhasel.
 860  */
 861 #define DMI_DMCONTROL_ACKHAVERESET_OFFSET   28
 862 #define DMI_DMCONTROL_ACKHAVERESET_LENGTH   1
 863 #define DMI_DMCONTROL_ACKHAVERESET          (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET)
 864 /*
 865 * Selects the  definition of currently selected harts.
 866 *
 867 * 0: There is a single currently selected hart, that selected by \Fhartsel.
 868 *
 869 * 1: There may be multiple currently selected harts -- that selected by \Fhartsel,
 870 * plus those selected by the hart array mask register.
 871 *
 872 * An implementation which does not implement the hart array mask register
 873 * must tie this field to 0. A debugger which wishes to use the hart array
 874 * mask register feature should set this bit and read back to see if the functionality
 875 * is supported.
 876  */
 877 #define DMI_DMCONTROL_HASEL_OFFSET          26
 878 #define DMI_DMCONTROL_HASEL_LENGTH          1
 879 #define DMI_DMCONTROL_HASEL                 (0x1U << DMI_DMCONTROL_HASEL_OFFSET)
 880 /*
 881 * The low 10 bits of \Fhartsel: the DM-specific index of the hart to
 882 * select. This hart is always part of the currently selected harts.
 883  */
 884 #define DMI_DMCONTROL_HARTSELLO_OFFSET      16
 885 #define DMI_DMCONTROL_HARTSELLO_LENGTH      10
 886 #define DMI_DMCONTROL_HARTSELLO             (0x3ffU << DMI_DMCONTROL_HARTSELLO_OFFSET)
 887 /*
 888 * The high 10 bits of \Fhartsel: the DM-specific index of the hart to
 889 * select. This hart is always part of the currently selected harts.
 890  */
 891 #define DMI_DMCONTROL_HARTSELHI_OFFSET      6
 892 #define DMI_DMCONTROL_HARTSELHI_LENGTH      10
 893 #define DMI_DMCONTROL_HARTSELHI             (0x3ffU << DMI_DMCONTROL_HARTSELHI_OFFSET)
 894 /*
 895 * This optional field writes the halt-on-reset request bit for all
 896 * currently selected harts.
 897 * When set to 1, each selected hart will halt upon the next deassertion
 898 * of its reset. The halt-on-reset request bit is not automatically
 899 * cleared. The debugger must write to \Fclrresethaltreq to clear it.
 900 *
 901 * Writes apply to the new value of \Fhartsel and \Fhasel.
 902 *
 903 * If \Fhasresethaltreq is 0, this field is not implemented.
 904  */
 905 #define DMI_DMCONTROL_SETRESETHALTREQ_OFFSET 3
 906 #define DMI_DMCONTROL_SETRESETHALTREQ_LENGTH 1
 907 #define DMI_DMCONTROL_SETRESETHALTREQ       (0x1U << DMI_DMCONTROL_SETRESETHALTREQ_OFFSET)
 908 /*
 909 * This optional field clears the halt-on-reset request bit for all
 910 * currently selected harts.
 911 *
 912 * Writes apply to the new value of \Fhartsel and \Fhasel.
 913  */
 914 #define DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET 2
 915 #define DMI_DMCONTROL_CLRRESETHALTREQ_LENGTH 1
 916 #define DMI_DMCONTROL_CLRRESETHALTREQ       (0x1U << DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET)
 917 /*
 918 * This bit controls the reset signal from the DM to the rest of the
 919 * system. The signal should reset every part of the system, including
 920 * every hart, except for the DM and any logic required to access the
 921 * DM.
 922 * To perform a system reset the debugger writes 1,
 923 * and then writes 0
 924 * to deassert the reset.
 925  */
 926 #define DMI_DMCONTROL_NDMRESET_OFFSET       1
 927 #define DMI_DMCONTROL_NDMRESET_LENGTH       1
 928 #define DMI_DMCONTROL_NDMRESET              (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET)
 929 /*
 930 * This bit serves as a reset signal for the Debug Module itself.
 931 *
 932 * 0: The module's state, including authentication mechanism,
 933 * takes its reset values (the \Fdmactive bit is the only bit which can
 934 * be written to something other than its reset value).
 935 *
 936 * 1: The module functions normally.
 937 *
 938 * No other mechanism should exist that may result in resetting the
 939 * Debug Module after power up, including the platform's system reset
 940 * or Debug Transport reset signals.
 941 *
 942 * A debugger may pulse this bit low to get the Debug Module into a
 943 * known state.
 944 *
 945 * Implementations may use this bit to aid debugging, for example by
 946 * preventing the Debug Module from being power gated while debugging
 947 * is active.
 948  */
 949 #define DMI_DMCONTROL_DMACTIVE_OFFSET       0
 950 #define DMI_DMCONTROL_DMACTIVE_LENGTH       1
 951 #define DMI_DMCONTROL_DMACTIVE              (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET)
 952 #define DMI_HARTINFO                        0x12
 953 /*
 954 * Number of {\tt dscratch} registers available for the debugger
 955 * to use during program buffer execution, starting from \Rdscratchzero.
 956 * The debugger can make no assumptions about the contents of these
 957 * registers between commands.
 958  */
 959 #define DMI_HARTINFO_NSCRATCH_OFFSET        20
 960 #define DMI_HARTINFO_NSCRATCH_LENGTH        4
 961 #define DMI_HARTINFO_NSCRATCH               (0xfU << DMI_HARTINFO_NSCRATCH_OFFSET)
 962 /*
 963 * 0: The {\tt data} registers are shadowed in the hart by CSR
 964 * registers. Each CSR register is MXLEN bits in size, and corresponds
 965 * to a single argument, per Table~\ref{tab:datareg}.
 966 *
 967 * 1: The {\tt data} registers are shadowed in the hart's memory map.
 968 * Each register takes up 4 bytes in the memory map.
 969  */
 970 #define DMI_HARTINFO_DATAACCESS_OFFSET      16
 971 #define DMI_HARTINFO_DATAACCESS_LENGTH      1
 972 #define DMI_HARTINFO_DATAACCESS             (0x1U << DMI_HARTINFO_DATAACCESS_OFFSET)
 973 /*
 974 * If \Fdataaccess is 0: Number of CSR registers dedicated to
 975 * shadowing the {\tt data} registers.
 976 *
 977 * If \Fdataaccess is 1: Number of 32-bit words in the memory map
 978 * dedicated to shadowing the {\tt data} registers.
 979 *
 980 * Since there are at most 12 {\tt data} registers, the value in this
 981 * register must be 12 or smaller.
 982  */
 983 #define DMI_HARTINFO_DATASIZE_OFFSET        12
 984 #define DMI_HARTINFO_DATASIZE_LENGTH        4
 985 #define DMI_HARTINFO_DATASIZE               (0xfU << DMI_HARTINFO_DATASIZE_OFFSET)
 986 /*
 987 * If \Fdataaccess is 0: The number of the first CSR dedicated to
 988 * shadowing the {\tt data} registers.
 989 *
 990 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
 991 * registers are shadowed, to be used to access relative to \Rzero.
 992  */
 993 #define DMI_HARTINFO_DATAADDR_OFFSET        0
 994 #define DMI_HARTINFO_DATAADDR_LENGTH        12
 995 #define DMI_HARTINFO_DATAADDR               (0xfffU << DMI_HARTINFO_DATAADDR_OFFSET)
 996 #define DMI_HAWINDOWSEL                     0x14
 997 /*
 998 * The high bits of this field may be tied to 0, depending on how large
 999 * the array mask register is.  Eg. on a system with 48 harts only bit 0
1000 * of this field may actually be writable.
1001  */
1002 #define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET  0
1003 #define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH  15
1004 #define DMI_HAWINDOWSEL_HAWINDOWSEL         (0x7fffU << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
1005 #define DMI_HAWINDOW                        0x15
1006 #define DMI_HAWINDOW_MASKDATA_OFFSET        0
1007 #define DMI_HAWINDOW_MASKDATA_LENGTH        32
1008 #define DMI_HAWINDOW_MASKDATA               (0xffffffffU << DMI_HAWINDOW_MASKDATA_OFFSET)
1009 #define DMI_ABSTRACTCS                      0x16
1010 /*
1011 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
1012  */
1013 #define DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET   24
1014 #define DMI_ABSTRACTCS_PROGBUFSIZE_LENGTH   5
1015 #define DMI_ABSTRACTCS_PROGBUFSIZE          (0x1fU << DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET)
1016 /*
1017 * 1: An abstract command is currently being executed.
1018 *
1019 * This bit is set as soon as \Rcommand is written, and is
1020 * not cleared until that command has completed.
1021  */
1022 #define DMI_ABSTRACTCS_BUSY_OFFSET          12
1023 #define DMI_ABSTRACTCS_BUSY_LENGTH          1
1024 #define DMI_ABSTRACTCS_BUSY                 (0x1U << DMI_ABSTRACTCS_BUSY_OFFSET)
1025 /*
1026 * Gets set if an abstract command fails. The bits in this field remain set until
1027 * they are cleared by writing 1 to them. No abstract command is
1028 * started until the value is reset to 0.
1029 *
1030 * 0 (none): No error.
1031 *
1032 * 1 (busy): An abstract command was executing while \Rcommand,
1033 * \Rabstractcs, \Rabstractauto was written, or when one
1034 * of the {\tt data} or {\tt progbuf} registers was read or written.
1035 *
1036 * 2 (not supported): The requested command is not supported,
1037 * regardless of whether the hart is running or not.
1038 *
1039 * 3 (exception): An exception occurred while executing the command
1040 * (eg. while executing the Program Buffer).
1041 *
1042 * 4 (halt/resume): The abstract command couldn't execute because the
1043 * hart wasn't in the required state (running/halted).
1044 *
1045 * 7 (other): The command failed for another reason.
1046  */
1047 #define DMI_ABSTRACTCS_CMDERR_OFFSET        8
1048 #define DMI_ABSTRACTCS_CMDERR_LENGTH        3
1049 #define DMI_ABSTRACTCS_CMDERR               (0x7U << DMI_ABSTRACTCS_CMDERR_OFFSET)
1050 /*
1051 * Number of {\tt data} registers that are implemented as part of the
1052 * abstract command interface. Valid sizes are 0 - 12.
1053  */
1054 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET     0
1055 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH     4
1056 #define DMI_ABSTRACTCS_DATACOUNT            (0xfU << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
1057 #define DMI_COMMAND                         0x17
1058 /*
1059 * The type determines the overall functionality of this
1060 * abstract command.
1061  */
1062 #define DMI_COMMAND_CMDTYPE_OFFSET          24
1063 #define DMI_COMMAND_CMDTYPE_LENGTH          8
1064 #define DMI_COMMAND_CMDTYPE                 (0xffU << DMI_COMMAND_CMDTYPE_OFFSET)
1065 /*
1066 * This field is interpreted in a command-specific manner,
1067 * described for each abstract command.
1068  */
1069 #define DMI_COMMAND_CONTROL_OFFSET          0
1070 #define DMI_COMMAND_CONTROL_LENGTH          24
1071 #define DMI_COMMAND_CONTROL                 (0xffffffU << DMI_COMMAND_CONTROL_OFFSET)
1072 #define DMI_ABSTRACTAUTO                    0x18
1073 /*
1074 * When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word
1075 * cause the command in \Rcommand to be executed again.
1076  */
1077 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
1078 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
1079 #define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF    (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
1080 /*
1081 * When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word
1082 * cause the command in \Rcommand to be executed again.
1083  */
1084 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
1085 #define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
1086 #define DMI_ABSTRACTAUTO_AUTOEXECDATA       (0xfffU << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
1087 #define DMI_DEVTREEADDR0                    0x19
1088 #define DMI_DEVTREEADDR0_ADDR_OFFSET        0
1089 #define DMI_DEVTREEADDR0_ADDR_LENGTH        32
1090 #define DMI_DEVTREEADDR0_ADDR               (0xffffffffU << DMI_DEVTREEADDR0_ADDR_OFFSET)
1091 #define DMI_DEVTREEADDR1                    0x1a
1092 #define DMI_DEVTREEADDR2                    0x1b
1093 #define DMI_DEVTREEADDR3                    0x1c
1094 #define DMI_NEXTDM                          0x1d
1095 #define DMI_NEXTDM_ADDR_OFFSET              0
1096 #define DMI_NEXTDM_ADDR_LENGTH              32
1097 #define DMI_NEXTDM_ADDR                     (0xffffffffU << DMI_NEXTDM_ADDR_OFFSET)
1098 #define DMI_DATA0                           0x04
1099 #define DMI_DATA0_DATA_OFFSET               0
1100 #define DMI_DATA0_DATA_LENGTH               32
1101 #define DMI_DATA0_DATA                      (0xffffffffU << DMI_DATA0_DATA_OFFSET)
1102 #define DMI_DATA11                          0x0f
1103 #define DMI_PROGBUF0                        0x20
1104 #define DMI_PROGBUF0_DATA_OFFSET            0
1105 #define DMI_PROGBUF0_DATA_LENGTH            32
1106 #define DMI_PROGBUF0_DATA                   (0xffffffffU << DMI_PROGBUF0_DATA_OFFSET)
1107 #define DMI_PROGBUF15                       0x2f
1108 #define DMI_AUTHDATA                        0x30
1109 #define DMI_AUTHDATA_DATA_OFFSET            0
1110 #define DMI_AUTHDATA_DATA_LENGTH            32
1111 #define DMI_AUTHDATA_DATA                   (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET)
1112 #define DMI_HALTSUM0                        0x40
1113 #define DMI_HALTSUM0_HALTSUM0_OFFSET        0
1114 #define DMI_HALTSUM0_HALTSUM0_LENGTH        32
1115 #define DMI_HALTSUM0_HALTSUM0               (0xffffffffU << DMI_HALTSUM0_HALTSUM0_OFFSET)
1116 #define DMI_HALTSUM1                        0x13
1117 #define DMI_HALTSUM1_HALTSUM1_OFFSET        0
1118 #define DMI_HALTSUM1_HALTSUM1_LENGTH        32
1119 #define DMI_HALTSUM1_HALTSUM1               (0xffffffffU << DMI_HALTSUM1_HALTSUM1_OFFSET)
1120 #define DMI_HALTSUM2                        0x34
1121 #define DMI_HALTSUM2_HALTSUM2_OFFSET        0
1122 #define DMI_HALTSUM2_HALTSUM2_LENGTH        32
1123 #define DMI_HALTSUM2_HALTSUM2               (0xffffffffU << DMI_HALTSUM2_HALTSUM2_OFFSET)
1124 #define DMI_HALTSUM3                        0x35
1125 #define DMI_HALTSUM3_HALTSUM3_OFFSET        0
1126 #define DMI_HALTSUM3_HALTSUM3_LENGTH        32
1127 #define DMI_HALTSUM3_HALTSUM3               (0xffffffffU << DMI_HALTSUM3_HALTSUM3_OFFSET)
1128 #define DMI_SBADDRESS3                      0x37
1129 /*
1130 * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
1131 * the system address bus is that wide).
1132  */
1133 #define DMI_SBADDRESS3_ADDRESS_OFFSET       0
1134 #define DMI_SBADDRESS3_ADDRESS_LENGTH       32
1135 #define DMI_SBADDRESS3_ADDRESS              (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET)
1136 #define DMI_SBCS                            0x38
1137 /*
1138 * 0: The System Bus interface conforms to mainline drafts of this
1139 * spec older than 1 January, 2018.
1140 *
1141 * 1: The System Bus interface conforms to this version of the spec.
1142 *
1143 * Other values are reserved for future versions.
1144  */
1145 #define DMI_SBCS_SBVERSION_OFFSET           29
1146 #define DMI_SBCS_SBVERSION_LENGTH           3
1147 #define DMI_SBCS_SBVERSION                  (0x7U << DMI_SBCS_SBVERSION_OFFSET)
1148 /*
1149 * Set when the debugger attempts to read data while a read is in
1150 * progress, or when the debugger initiates a new access while one is
1151 * already in progress (while \Fsbbusy is set). It remains set until
1152 * it's explicitly cleared by the debugger.
1153 *
1154 * While this field is non-zero, no more system bus accesses can be
1155 * initiated by the Debug Module.
1156  */
1157 #define DMI_SBCS_SBBUSYERROR_OFFSET         22
1158 #define DMI_SBCS_SBBUSYERROR_LENGTH         1
1159 #define DMI_SBCS_SBBUSYERROR                (0x1U << DMI_SBCS_SBBUSYERROR_OFFSET)
1160 /*
1161 * When 1, indicates the system bus master is busy. (Whether the
1162 * system bus itself is busy is related, but not the same thing.) This
1163 * bit goes high immediately when a read or write is requested for any
1164 * reason, and does not go low until the access is fully completed.
1165 *
1166 * Writes to \Rsbcs while \Fsbbusy is high result in undefined
1167 * behavior.  A debugger must not write to \Rsbcs until it reads
1168 * \Fsbbusy as 0.
1169  */
1170 #define DMI_SBCS_SBBUSY_OFFSET              21
1171 #define DMI_SBCS_SBBUSY_LENGTH              1
1172 #define DMI_SBCS_SBBUSY                     (0x1U << DMI_SBCS_SBBUSY_OFFSET)
1173 /*
1174 * When 1, every write to \Rsbaddresszero automatically triggers a
1175 * system bus read at the new address.
1176  */
1177 #define DMI_SBCS_SBREADONADDR_OFFSET        20
1178 #define DMI_SBCS_SBREADONADDR_LENGTH        1
1179 #define DMI_SBCS_SBREADONADDR               (0x1U << DMI_SBCS_SBREADONADDR_OFFSET)
1180 /*
1181 * Select the access size to use for system bus accesses.
1182 *
1183 * 0: 8-bit
1184 *
1185 * 1: 16-bit
1186 *
1187 * 2: 32-bit
1188 *
1189 * 3: 64-bit
1190 *
1191 * 4: 128-bit
1192 *
1193 * If \Fsbaccess has an unsupported value when the DM starts a bus
1194 * access, the access is not performed and \Fsberror is set to 3.
1195  */
1196 #define DMI_SBCS_SBACCESS_OFFSET            17
1197 #define DMI_SBCS_SBACCESS_LENGTH            3
1198 #define DMI_SBCS_SBACCESS                   (0x7U << DMI_SBCS_SBACCESS_OFFSET)
1199 /*
1200 * When 1, {\tt sbaddress} is incremented by the access size (in
1201 * bytes) selected in \Fsbaccess after every system bus access.
1202  */
1203 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET     16
1204 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH     1
1205 #define DMI_SBCS_SBAUTOINCREMENT            (0x1U << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
1206 /*
1207 * When 1, every read from \Rsbdatazero automatically triggers a
1208 * system bus read at the (possibly auto-incremented) address.
1209  */
1210 #define DMI_SBCS_SBREADONDATA_OFFSET        15
1211 #define DMI_SBCS_SBREADONDATA_LENGTH        1
1212 #define DMI_SBCS_SBREADONDATA               (0x1U << DMI_SBCS_SBREADONDATA_OFFSET)
1213 /*
1214 * When the Debug Module's system bus
1215 * master causes a bus error, this field gets set. The bits in this
1216 * field remain set until they are cleared by writing 1 to them.
1217 * While this field is non-zero, no more system bus accesses can be
1218 * initiated by the Debug Module.
1219 *
1220 * An implementation may report "Other" (7) for any error condition.
1221 *
1222 * 0: There was no bus error.
1223 *
1224 * 1: There was a timeout.
1225 *
1226 * 2: A bad address was accessed.
1227 *
1228 * 3: There was an alignment error.
1229 *
1230 * 4: An access of unsupported size was requested.
1231 *
1232 * 7: Other.
1233  */
1234 #define DMI_SBCS_SBERROR_OFFSET             12
1235 #define DMI_SBCS_SBERROR_LENGTH             3
1236 #define DMI_SBCS_SBERROR                    (0x7U << DMI_SBCS_SBERROR_OFFSET)
1237 /*
1238 * Width of system bus addresses in bits. (0 indicates there is no bus
1239 * access support.)
1240  */
1241 #define DMI_SBCS_SBASIZE_OFFSET             5
1242 #define DMI_SBCS_SBASIZE_LENGTH             7
1243 #define DMI_SBCS_SBASIZE                    (0x7fU << DMI_SBCS_SBASIZE_OFFSET)
1244 /*
1245 * 1 when 128-bit system bus accesses are supported.
1246  */
1247 #define DMI_SBCS_SBACCESS128_OFFSET         4
1248 #define DMI_SBCS_SBACCESS128_LENGTH         1
1249 #define DMI_SBCS_SBACCESS128                (0x1U << DMI_SBCS_SBACCESS128_OFFSET)
1250 /*
1251 * 1 when 64-bit system bus accesses are supported.
1252  */
1253 #define DMI_SBCS_SBACCESS64_OFFSET          3
1254 #define DMI_SBCS_SBACCESS64_LENGTH          1
1255 #define DMI_SBCS_SBACCESS64                 (0x1U << DMI_SBCS_SBACCESS64_OFFSET)
1256 /*
1257 * 1 when 32-bit system bus accesses are supported.
1258  */
1259 #define DMI_SBCS_SBACCESS32_OFFSET          2
1260 #define DMI_SBCS_SBACCESS32_LENGTH          1
1261 #define DMI_SBCS_SBACCESS32                 (0x1U << DMI_SBCS_SBACCESS32_OFFSET)
1262 /*
1263 * 1 when 16-bit system bus accesses are supported.
1264  */
1265 #define DMI_SBCS_SBACCESS16_OFFSET          1
1266 #define DMI_SBCS_SBACCESS16_LENGTH          1
1267 #define DMI_SBCS_SBACCESS16                 (0x1U << DMI_SBCS_SBACCESS16_OFFSET)
1268 /*
1269 * 1 when 8-bit system bus accesses are supported.
1270  */
1271 #define DMI_SBCS_SBACCESS8_OFFSET           0
1272 #define DMI_SBCS_SBACCESS8_LENGTH           1
1273 #define DMI_SBCS_SBACCESS8                  (0x1U << DMI_SBCS_SBACCESS8_OFFSET)
1274 #define DMI_SBADDRESS0                      0x39
1275 /*
1276 * Accesses bits 31:0 of the physical address in {\tt sbaddress}.
1277  */
1278 #define DMI_SBADDRESS0_ADDRESS_OFFSET       0
1279 #define DMI_SBADDRESS0_ADDRESS_LENGTH       32
1280 #define DMI_SBADDRESS0_ADDRESS              (0xffffffffU << DMI_SBADDRESS0_ADDRESS_OFFSET)
1281 #define DMI_SBADDRESS1                      0x3a
1282 /*
1283 * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
1284 * the system address bus is that wide).
1285  */
1286 #define DMI_SBADDRESS1_ADDRESS_OFFSET       0
1287 #define DMI_SBADDRESS1_ADDRESS_LENGTH       32
1288 #define DMI_SBADDRESS1_ADDRESS              (0xffffffffU << DMI_SBADDRESS1_ADDRESS_OFFSET)
1289 #define DMI_SBADDRESS2                      0x3b
1290 /*
1291 * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
1292 * the system address bus is that wide).
1293  */
1294 #define DMI_SBADDRESS2_ADDRESS_OFFSET       0
1295 #define DMI_SBADDRESS2_ADDRESS_LENGTH       32
1296 #define DMI_SBADDRESS2_ADDRESS              (0xffffffffU << DMI_SBADDRESS2_ADDRESS_OFFSET)
1297 #define DMI_SBDATA0                         0x3c
1298 /*
1299 * Accesses bits 31:0 of {\tt sbdata}.
1300  */
1301 #define DMI_SBDATA0_DATA_OFFSET             0
1302 #define DMI_SBDATA0_DATA_LENGTH             32
1303 #define DMI_SBDATA0_DATA                    (0xffffffffU << DMI_SBDATA0_DATA_OFFSET)
1304 #define DMI_SBDATA1                         0x3d
1305 /*
1306 * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
1307 * wide).
1308  */
1309 #define DMI_SBDATA1_DATA_OFFSET             0
1310 #define DMI_SBDATA1_DATA_LENGTH             32
1311 #define DMI_SBDATA1_DATA                    (0xffffffffU << DMI_SBDATA1_DATA_OFFSET)
1312 #define DMI_SBDATA2                         0x3e
1313 /*
1314 * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
1315 * wide).
1316  */
1317 #define DMI_SBDATA2_DATA_OFFSET             0
1318 #define DMI_SBDATA2_DATA_LENGTH             32
1319 #define DMI_SBDATA2_DATA                    (0xffffffffU << DMI_SBDATA2_DATA_OFFSET)
1320 #define DMI_SBDATA3                         0x3f
1321 /*
1322 * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
1323 * wide).
1324  */
1325 #define DMI_SBDATA3_DATA_OFFSET             0
1326 #define DMI_SBDATA3_DATA_LENGTH             32
1327 #define DMI_SBDATA3_DATA                    (0xffffffffU << DMI_SBDATA3_DATA_OFFSET)
1328 #define SHORTNAME                           0x123
1329 /*
1330 * Description of what this field is used for.
1331  */
1332 #define SHORTNAME_FIELD_OFFSET              0
1333 #define SHORTNAME_FIELD_LENGTH              8
1334 #define SHORTNAME_FIELD                     (0xffU << SHORTNAME_FIELD_OFFSET)
1335 #define AC_ACCESS_REGISTER                  None
1336 /*
1337 * This is 0 to indicate Access Register Command.
1338  */
1339 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET   24
1340 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH   8
1341 #define AC_ACCESS_REGISTER_CMDTYPE          (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
1342 /*
1343 * 2: Access the lowest 32 bits of the register.
1344 *
1345 * 3: Access the lowest 64 bits of the register.
1346 *
1347 * 4: Access the lowest 128 bits of the register.
1348 *
1349 * If \Fsize specifies a size larger than the register's actual size,
1350 * then the access must fail. If a register is accessible, then reads of \Fsize
1351 * less than or equal to the register's actual size must be supported.
1352 *
1353 * This field controls the Argument Width as referenced in
1354 * Table~\ref{tab:datareg}.
1355  */
1356 #define AC_ACCESS_REGISTER_SIZE_OFFSET      20
1357 #define AC_ACCESS_REGISTER_SIZE_LENGTH      3
1358 #define AC_ACCESS_REGISTER_SIZE             (0x7U << AC_ACCESS_REGISTER_SIZE_OFFSET)
1359 /*
1360 * When 1, execute the program in the Program Buffer exactly once
1361 * after performing the transfer, if any.
1362  */
1363 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET  18
1364 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH  1
1365 #define AC_ACCESS_REGISTER_POSTEXEC         (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1366 /*
1367 * 0: Don't do the operation specified by \Fwrite.
1368 *
1369 * 1: Do the operation specified by \Fwrite.
1370 *
1371 * This bit can be used to just execute the Program Buffer without
1372 * having to worry about placing valid values into \Fsize or \Fregno.
1373  */
1374 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET  17
1375 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH  1
1376 #define AC_ACCESS_REGISTER_TRANSFER         (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
1377 /*
1378 * When \Ftransfer is set:
1379 * 0: Copy data from the specified register into {\tt arg0} portion
1380 * of {\tt data}.
1381 *
1382 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1383 * specified register.
1384  */
1385 #define AC_ACCESS_REGISTER_WRITE_OFFSET     16
1386 #define AC_ACCESS_REGISTER_WRITE_LENGTH     1
1387 #define AC_ACCESS_REGISTER_WRITE            (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET)
1388 /*
1389 * Number of the register to access, as described in
1390 * Table~\ref{tab:regno}.
1391 * \Rdpc may be used as an alias for PC if this command is
1392 * supported on a non-halted hart.
1393  */
1394 #define AC_ACCESS_REGISTER_REGNO_OFFSET     0
1395 #define AC_ACCESS_REGISTER_REGNO_LENGTH     16
1396 #define AC_ACCESS_REGISTER_REGNO            (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET)
1397 #define AC_QUICK_ACCESS                     None
1398 /*
1399 * This is 1 to indicate Quick Access command.
1400  */
1401 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET      24
1402 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH      8
1403 #define AC_QUICK_ACCESS_CMDTYPE             (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET)
1404 #define VIRT_PRIV                           virtual
1405 /*
1406 * Contains the privilege level the hart was operating in when Debug
1407 * Mode was entered. The encoding is described in Table
1408 * \ref{tab:privlevel}, and matches the privilege level encoding from
1409 * the RISC-V Privileged ISA Specification. A user can write this
1410 * value to change the hart's privilege level when exiting Debug Mode.
1411  */
1412 #define VIRT_PRIV_PRV_OFFSET                0
1413 #define VIRT_PRIV_PRV_LENGTH                2
1414 #define VIRT_PRIV_PRV                       (0x3U << VIRT_PRIV_PRV_OFFSET)