riscv/debug_module.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_DEBUG_MODULE_H
   3 #define _RISCV_DEBUG_MODULE_H
   4
   5 #include <set>
   6
   7 #include "devices.h"
   8
   9 class sim_t;
  10
  11 typedef struct {
  12   bool haltreq;
  13   bool resumereq;
  14   unsigned hartsel;
  15   bool hartreset;
  16   bool dmactive;
  17   bool ndmreset;
  18 } dmcontrol_t;
  19
  20 typedef struct {
  21   bool impebreak;
  22   bool allhavereset;
  23   bool anyhavereset;
  24   bool allnonexistant;
  25   bool anynonexistant;
  26   bool allunavail;
  27   bool anyunavail;
  28   bool allrunning;
  29   bool anyrunning;
  30   bool allhalted;
  31   bool anyhalted;
  32   bool allresumeack;
  33   bool anyresumeack;
  34   bool authenticated;
  35   bool authbusy;
  36   bool cfgstrvalid;
  37   unsigned version;
  38 } dmstatus_t;
  39
  40 typedef enum cmderr {
  41     CMDERR_NONE = 0,
  42     CMDERR_BUSY = 1,
  43     CMDERR_NOTSUP = 2,
  44     CMDERR_EXCEPTION = 3,
  45     CMDERR_HALTRESUME = 4,
  46     CMDERR_OTHER = 7
  47 } cmderr_t;
  48
  49 typedef struct {
  50   bool busy;
  51   unsigned datacount;
  52   unsigned progbufsize;
  53   cmderr_t cmderr;
  54 } abstractcs_t;
  55
  56 typedef struct {
  57   unsigned autoexecprogbuf;
  58   unsigned autoexecdata;
  59 } abstractauto_t;
  60
  61 typedef struct {
  62   unsigned version;
  63   bool readonaddr;
  64   unsigned sbaccess;
  65   bool autoincrement;
  66   bool readondata;
  67   unsigned error;
  68   unsigned asize;
  69   bool access128;
  70   bool access64;
  71   bool access32;
  72   bool access16;
  73   bool access8;
  74 } sbcs_t;
  75
  76 class debug_module_t : public abstract_device_t
  77 {
  78   public:
  79     /*
  80      * If require_authentication is true, then a debugger must authenticate as
  81      * follows:
  82      * 1. Read a 32-bit value from authdata:
  83      * 2. Write the value that was read back, plus one, to authdata.
  84      */
  85     debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
  86         bool require_authentication);
  87     ~debug_module_t();
  88
  89     void add_device(bus_t *bus);
  90
  91     bool load(reg_t addr, size_t len, uint8_t* bytes);
  92     bool store(reg_t addr, size_t len, const uint8_t* bytes);
  93
  94     // Debug Module Interface that the debugger (in our case through JTAG DTM)
  95     // uses to access the DM.
  96     // Return true for success, false for failure.
  97     bool dmi_read(unsigned address, uint32_t *value);
  98     bool dmi_write(unsigned address, uint32_t value);
  99
 100     // Called when one of the attached harts was reset.
 101     void proc_reset(unsigned id);
 102
 103   private:
 104     static const unsigned datasize = 2;
 105     // Size of program_buffer in 32-bit words, as exposed to the rest of the
 106     // world.
 107     unsigned progbufsize;
 108     // Actual size of the program buffer, which is 1 word bigger than we let on
 109     // to implement the implicit ebreak at the end.
 110     unsigned program_buffer_bytes;
 111     unsigned max_bus_master_bits;
 112     bool require_authentication;
 113     static const unsigned debug_data_start = 0x380;
 114     unsigned debug_progbuf_start;
 115
 116     static const unsigned debug_abstract_size = 5;
 117     unsigned debug_abstract_start;
 118     // R/W this through custom registers, to allow debuggers to test that
 119     // functionality.
 120     unsigned custom_base;
 121
 122     // We only support 1024 harts currently. More requires at least resizing
 123     // the arrays below, and their corresponding special memory regions.
 124     static const unsigned hartsellen = 10;
 125
 126     sim_t *sim;
 127
 128     uint8_t debug_rom_whereto[4];
 129     uint8_t debug_abstract[debug_abstract_size * 4];
 130     uint8_t *program_buffer;
 131     uint8_t dmdata[datasize * 4];
 132
 133     bool halted[1024];
 134     bool resumeack[1024];
 135     bool havereset[1024];
 136     uint8_t debug_rom_flags[1024];
 137
 138     void write32(uint8_t *rom, unsigned int index, uint32_t value);
 139     uint32_t read32(uint8_t *rom, unsigned int index);
 140
 141     void sb_autoincrement();
 142     void sb_read();
 143     void sb_write();
 144     unsigned sb_access_bits();
 145
 146     dmcontrol_t dmcontrol;
 147     dmstatus_t dmstatus;
 148     abstractcs_t abstractcs;
 149     abstractauto_t abstractauto;
 150     uint32_t command;
 151
 152     sbcs_t sbcs;
 153     uint32_t sbaddress[4];
 154     uint32_t sbdata[4];
 155
 156     uint32_t challenge;
 157     const uint32_t secret = 1;
 158
 159     processor_t *current_proc() const;
 160     void reset();
 161     bool perform_abstract_command();
 162 };
 163
 164 #endif