riscv/sim.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIM_H
   4 #define _RISCV_SIM_H
   5
   6 #include "processor.h"
   7 #include "devices.h"
   8 #include "debug_module.h"
   9 #include "simif.h"
  10 #include <fesvr/htif.h>
  11 #include <fesvr/context.h>
  12 #include <vector>
  13 #include <string>
  14 #include <memory>
  15
  16 class mmu_t;
  17 class remote_bitbang_t;
  18
  19 // this class encapsulates the processors and memory in a RISC-V machine.
  20 class sim_t : public htif_t, public simif_t
  21 {
  22 public:
  23   sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
  24         std::vector<std::pair<reg_t, mem_t*>> mems,
  25         const std::vector<std::string>& args, const std::vector<int> hartids,
  26         unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
  27   ~sim_t();
  28
  29   // run the simulation to completion
  30   int run();
  31   void set_debug(bool value);
  32   void set_log(bool value);
  33   void set_histogram(bool value);
  34   void set_procs_debug(bool value);
  35   void set_dtb_enabled(bool value) {
  36     this->dtb_enabled = value;
  37   }
  38   void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
  39     this->remote_bitbang = remote_bitbang;
  40   }
  41   const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); }
  42   processor_t* get_core(size_t i) { return procs.at(i); }
  43   unsigned nprocs() const { return procs.size(); }
  44
  45   // Callback for processors to let the simulation know they were reset.
  46   void proc_reset(unsigned id);
  47
  48 private:
  49   std::vector<std::pair<reg_t, mem_t*>> mems;
  50   mmu_t* debug_mmu;  // debug port into main memory
  51   std::vector<processor_t*> procs;
  52   reg_t start_pc;
  53   std::string dts;
  54   std::unique_ptr<rom_device_t> boot_rom;
  55   std::unique_ptr<clint_t> clint;
  56   bus_t bus;
  57
  58   processor_t* get_core(const std::string& i);
  59   void step(size_t n); // step through simulation
  60   static const size_t INTERLEAVE = 5000;
  61   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
  62   static const size_t CPU_HZ = 1000000000; // 1GHz CPU
  63   size_t current_step;
  64   size_t current_proc;
  65   bool debug;
  66   bool log;
  67   bool histogram_enabled; // provide a histogram of PCs
  68   bool dtb_enabled;
  69   remote_bitbang_t* remote_bitbang;
  70
  71   // memory-mapped I/O routines
  72   char* addr_to_mem(reg_t addr);
  73   bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
  74   bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
  75   void make_dtb();
  76
  77   // presents a prompt for introspection into the simulation
  78   void interactive();
  79
  80   // functions that help implement interactive()
  81   void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
  82   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
  83   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
  84   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
  85   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
  86   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
  87   void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
  88   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
  89   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
  90   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
  91   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
  92   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
  93   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
  94   reg_t get_reg(const std::vector<std::string>& args);
  95   freg_t get_freg(const std::vector<std::string>& args);
  96   reg_t get_mem(const std::vector<std::string>& args);
  97   reg_t get_pc(const std::vector<std::string>& args);
  98
  99   friend class processor_t;
 100   friend class mmu_t;
 101   friend class debug_module_t;
 102
 103   // htif
 104   friend void sim_thread_main(void*);
 105   void main();
 106
 107   context_t* host;
 108   context_t target;
 109   void reset();
 110   void idle();
 111   void read_chunk(addr_t taddr, size_t len, void* dst);
 112   void write_chunk(addr_t taddr, size_t len, const void* src);
 113   size_t chunk_align() { return 8; }
 114   size_t chunk_max_size() { return 8; }
 115
 116 public:
 117   // Initialize this after procs, because in debug_module_t::reset() we
 118   // enumerate processors, which segfaults if procs hasn't been initialized
 119   // yet.
 120   debug_module_t debug_module;
 121 };
 122
 123 extern volatile bool ctrlc_pressed;
 124
 125 #endif