Make the debug tests aware of multicore.
[riscv-tests.git] / debug / programs / entry.S
1 #ifndef ENTRY_S
2 #define ENTRY_S
3
4 #include "encoding.h"
5
6 #define STACK_SIZE 512
7
8 #if XLEN == 64
9 # define LREG ld
10 # define SREG sd
11 # define REGBYTES 8
12 #else
13 # define LREG lw
14 # define SREG sw
15 # define REGBYTES 4
16 #endif
17
18 .section .text.entry
19 .globl _start
20 _start:
21 j handle_reset
22
23 nmi_vector:
24 j nmi_vector
25
26 trap_vector:
27 j trap_entry
28
29 handle_reset:
30 // If misa doesn't exist (or is following an old spec where it has a
31 // different number), skip the next block.
32 la t0, 3f
33 csrw mtvec, t0
34 csrwi mstatus, 0
35
36 // make sure these registers exist by seeing if either S or U bits
37 // are set before attempting to zero them out.
38 csrr t1, misa
39 addi t2, x0, 1
40 slli t2, t2, 20 // U_EXTENSION
41 and t2, t1, t2
42 bne x0, t2, 1f
43 addi t2, x0, 1
44 slli t2, t2, 18 // S_EXTENSION
45 and t2, t1, t2
46 bne x0, t2, 1f
47 j 2f
48 1:
49 csrwi mideleg, 0
50 csrwi medeleg, 0
51 2:
52 csrwi mie, 0
53 3:
54 la t0, trap_entry
55 csrw mtvec, t0
56 csrwi mstatus, 0
57
58 # initialize global pointer
59 .option push
60 .option norelax
61 la gp, __global_pointer$
62 .option pop
63
64 # initialize stack pointer
65 la sp, stack_top
66
67 # Clear all hardware triggers
68 li t0, ~0
69 1:
70 addi t0, t0, 1
71 csrw CSR_TSELECT, t0
72 csrw CSR_TDATA1, zero
73 csrr t1, CSR_TSELECT
74 beq t0, t1, 1b
75
76 # perform the rest of initialization in C
77 j _init
78
79
80 trap_entry:
81 addi sp, sp, -32*REGBYTES
82
83 SREG x1, 1*REGBYTES(sp)
84 SREG x2, 2*REGBYTES(sp)
85 SREG x3, 3*REGBYTES(sp)
86 SREG x4, 4*REGBYTES(sp)
87 SREG x5, 5*REGBYTES(sp)
88 SREG x6, 6*REGBYTES(sp)
89 SREG x7, 7*REGBYTES(sp)
90 SREG x8, 8*REGBYTES(sp)
91 SREG x9, 9*REGBYTES(sp)
92 SREG x10, 10*REGBYTES(sp)
93 SREG x11, 11*REGBYTES(sp)
94 SREG x12, 12*REGBYTES(sp)
95 SREG x13, 13*REGBYTES(sp)
96 SREG x14, 14*REGBYTES(sp)
97 SREG x15, 15*REGBYTES(sp)
98 SREG x16, 16*REGBYTES(sp)
99 SREG x17, 17*REGBYTES(sp)
100 SREG x18, 18*REGBYTES(sp)
101 SREG x19, 19*REGBYTES(sp)
102 SREG x20, 20*REGBYTES(sp)
103 SREG x21, 21*REGBYTES(sp)
104 SREG x22, 22*REGBYTES(sp)
105 SREG x23, 23*REGBYTES(sp)
106 SREG x24, 24*REGBYTES(sp)
107 SREG x25, 25*REGBYTES(sp)
108 SREG x26, 26*REGBYTES(sp)
109 SREG x27, 27*REGBYTES(sp)
110 SREG x28, 28*REGBYTES(sp)
111 SREG x29, 29*REGBYTES(sp)
112 SREG x30, 30*REGBYTES(sp)
113 SREG x31, 31*REGBYTES(sp)
114
115 csrr a0, mcause
116 csrr a1, mepc
117 mv a2, sp
118 jal handle_trap
119 csrw mepc, a0
120
121 # Remain in M-mode after mret
122 li t0, MSTATUS_MPP
123 csrs mstatus, t0
124
125 LREG x1, 1*REGBYTES(sp)
126 LREG x2, 2*REGBYTES(sp)
127 LREG x3, 3*REGBYTES(sp)
128 LREG x4, 4*REGBYTES(sp)
129 LREG x5, 5*REGBYTES(sp)
130 LREG x6, 6*REGBYTES(sp)
131 LREG x7, 7*REGBYTES(sp)
132 LREG x8, 8*REGBYTES(sp)
133 LREG x9, 9*REGBYTES(sp)
134 LREG x10, 10*REGBYTES(sp)
135 LREG x11, 11*REGBYTES(sp)
136 LREG x12, 12*REGBYTES(sp)
137 LREG x13, 13*REGBYTES(sp)
138 LREG x14, 14*REGBYTES(sp)
139 LREG x15, 15*REGBYTES(sp)
140 LREG x16, 16*REGBYTES(sp)
141 LREG x17, 17*REGBYTES(sp)
142 LREG x18, 18*REGBYTES(sp)
143 LREG x19, 19*REGBYTES(sp)
144 LREG x20, 20*REGBYTES(sp)
145 LREG x21, 21*REGBYTES(sp)
146 LREG x22, 22*REGBYTES(sp)
147 LREG x23, 23*REGBYTES(sp)
148 LREG x24, 24*REGBYTES(sp)
149 LREG x25, 25*REGBYTES(sp)
150 LREG x26, 26*REGBYTES(sp)
151 LREG x27, 27*REGBYTES(sp)
152 LREG x28, 28*REGBYTES(sp)
153 LREG x29, 29*REGBYTES(sp)
154 LREG x30, 30*REGBYTES(sp)
155 LREG x31, 31*REGBYTES(sp)
156
157 addi sp, sp, 32*REGBYTES
158 mret
159
160 loop_forever:
161 j loop_forever
162
163 // Fill the stack with data so we can see if it was overrun.
164 .align 4
165 stack_bottom:
166 .fill STACK_SIZE/4, 4, 0x22446688
167 stack_top:
168 // Prevent stack_top from being identical to next symbol, which may cause gdb
169 // to report we're halted at stack_top which happens to be the same address
170 // as main.
171 .word 0
172 #endif