debug/targets.py

   1 import os.path
   2 import tempfile
   3
   4 import testlib
   5
   6 class Target(object):
   7     name = "name"
   8     xlen = 0
   9     directory = None
  10     timeout_sec = 2
  11     temporary_files = []
  12     temporary_binary = None
  13     openocd_config = []
  14     use_fpu = False
  15     misa = None
  16
  17     def __init__(self, server_cmd, sim_cmd, isolate):
  18         self.server_cmd = server_cmd
  19         self.sim_cmd = sim_cmd
  20         self.isolate = isolate
  21
  22     def target(self):
  23         """Start the target, eg. a simulator."""
  24         pass
  25
  26     def server(self):
  27         """Start the debug server that gdb connects to, eg. OpenOCD."""
  28         if self.openocd_config:
  29             return testlib.Openocd(server_cmd=self.server_cmd,
  30                     config=self.openocd_config)
  31         else:
  32             raise NotImplementedError
  33
  34     def compile(self, *sources):
  35         binary_name = "%s_%s-%d" % (
  36                 self.name,
  37                 os.path.basename(os.path.splitext(sources[0])[0]),
  38                 self.xlen)
  39         if self.isolate:
  40             self.temporary_binary = tempfile.NamedTemporaryFile(
  41                     prefix=binary_name + "_")
  42             binary_name = self.temporary_binary.name
  43             Target.temporary_files.append(self.temporary_binary)
  44         march = "rv%dima" % self.xlen
  45         if self.use_fpu:
  46             march += "fd"
  47         if self.extensionSupported("c"):
  48             march += "c"
  49         testlib.compile(sources +
  50                 ("programs/entry.S", "programs/init.c",
  51                     "-I", "../env",
  52                     "-march=%s" % march,
  53                     "-T", "targets/%s/link.lds" % (self.directory or self.name),
  54                     "-nostartfiles",
  55                     "-mcmodel=medany",
  56                     "-DXLEN=%d" % self.xlen,
  57                     "-o", binary_name),
  58                 xlen=self.xlen)
  59         return binary_name
  60
  61     def extensionSupported(self, letter):
  62         # target.misa is set by testlib.ExamineTarget
  63         return self.misa & (1 << (ord(letter.upper()) - ord('A')))
  64
  65 class SpikeTarget(Target):
  66     # pylint: disable=abstract-method
  67     directory = "spike"
  68     ram = 0x10000000
  69     ram_size = 0x10000000
  70     instruction_hardware_breakpoint_count = 4
  71     reset_vector = 0x1000
  72     openocd_config = "targets/%s/openocd.cfg" % directory
  73
  74 class Spike64Target(SpikeTarget):
  75     name = "spike64"
  76     xlen = 64
  77     use_fpu = True
  78
  79     def target(self):
  80         return testlib.Spike(self.sim_cmd)
  81
  82 class Spike32Target(SpikeTarget):
  83     name = "spike32"
  84     xlen = 32
  85
  86     def target(self):
  87         return testlib.Spike(self.sim_cmd, xlen=32)
  88
  89 class FreedomE300Target(Target):
  90     name = "freedom-e300"
  91     xlen = 32
  92     ram = 0x80000000
  93     ram_size = 16 * 1024
  94     instruction_hardware_breakpoint_count = 2
  95     openocd_config = "targets/%s/openocd.cfg" % name
  96
  97 class HiFive1Target(FreedomE300Target):
  98     name = "HiFive1"
  99     openocd_config = "targets/%s/openocd.cfg" % name
 100
 101 class FreedomE300SimTarget(Target):
 102     name = "freedom-e300-sim"
 103     xlen = 32
 104     timeout_sec = 6000
 105     ram = 0x80000000
 106     ram_size = 256 * 1024 * 1024
 107     instruction_hardware_breakpoint_count = 2
 108     openocd_config = "targets/%s/openocd.cfg" % name
 109
 110     def target(self):
 111         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 112
 113 class FreedomU500Target(Target):
 114     name = "freedom-u500"
 115     xlen = 64
 116     ram = 0x80000000
 117     ram_size = 16 * 1024
 118     instruction_hardware_breakpoint_count = 2
 119     openocd_config = "targets/%s/openocd.cfg" % name
 120
 121 class FreedomU500SimTarget(Target):
 122     name = "freedom-u500-sim"
 123     xlen = 64
 124     timeout_sec = 6000
 125     ram = 0x80000000
 126     ram_size = 256 * 1024 * 1024
 127     instruction_hardware_breakpoint_count = 2
 128     openocd_config = "targets/%s/openocd.cfg" % name
 129
 130     def target(self):
 131         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 132
 133 targets = [
 134         Spike32Target,
 135         Spike64Target,
 136         FreedomE300Target,
 137         FreedomU500Target,
 138         FreedomE300SimTarget,
 139         FreedomU500SimTarget,
 140         HiFive1Target]
 141
 142 def add_target_options(parser):
 143     group = parser.add_mutually_exclusive_group(required=True)
 144     for t in targets:
 145         group.add_argument("--%s" % t.name, action="store_const", const=t,
 146                 dest="target")
 147     parser.add_argument("--sim_cmd",
 148             help="The command to use to start the actual target (e.g. "
 149             "simulation)")
 150     parser.add_argument("--server_cmd",
 151             help="The command to use to start the debug server (e.g. OpenOCD)")
 152
 153     xlen_group = parser.add_mutually_exclusive_group()
 154     xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",
 155             help="Force the target to be 32-bit.")
 156     xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen",
 157             help="Force the target to be 64-bit.")
 158
 159     parser.add_argument("--isolate", action="store_true",
 160             help="Try to run in such a way that multiple instances can run at "
 161             "the same time. This may make it harder to debug a failure if it "
 162             "does occur.")