Merge pull request #55 from riscv/debug
[riscv-tests.git] / debug / targets / RISC-V / spike64.py
1 import targets
2 import testlib
3
4 class spike64(targets.Target):
5 xlen = 64
6 ram = 0x1212340000
7 ram_size = 0x10000000
8 instruction_hardware_breakpoint_count = 4
9 reset_vector = 0x1000
10
11 def create(self):
12 return testlib.Spike(self)